ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 18

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
•
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DACCRAM Address Register
This 7-bit register provides the address to the internal RAM when doing indirect writes/reads to the DAC Coefficient
RAM.
DACCRAM STATUS Register
This control register provides the write/read enable when doing indirect writes/reads to the DAC Coefficient RAM.
R64 (40h)
DACCRADDR
R138 (8Ah)
DACCRSTAT
Register Address
Register Address
Generic write operation
EQ RAM write operation
SDA
SCL
3.4.3.
S
S
DA[6:0], W
DA6
Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM
The DAC Coefficient RAM is a single port 161x24 synchronous RAM. It is programmed indirectly
through the Control Bus in the following manner:
1. Write target address to DACCRAM_ADDR register.
2. Write D7:0 to the DACCRAM_WRITE_LO register
3. Write D15:8 to the DACCRAM_WRITE_MID register
4. Write D23:16 to the DACCRAM_WRITE_HI register
5. On successful receipt of the DACCRAM_WRITE_HI data, the part will automatically start a write
6. On completion of the internal write cycle, the DACCRAM_Busy bit will be 0 (when operating the
7. The bus cycle may be terminated by the host or steps 2-6 may be repeated for writes to consec-
RA[7:0]
write
cycle. The DACCRAM_Busy bit will be set high to indicate that a write is in progress.
control interface at high speeds - TBD - software must poll this bit to ensure the write cycle is
complete before starting another write cycle.)
utive EQ RAM locations.
DA0
Bit
7:0
Bit
6:0
EQ RAM Address
7
W
DACCRAM_Busy
RD[7:0]
DACCRADD
A
RSVD
Label
Label
S
EQ_A updated;
EQ RAM read req = 1
Figure 6.
S
DA[6:0], W
Table 11. DACCRAM Address Register
RA7
Table 12. DACCRAM Status Register
repeat for multiple consecutive EQ RAM locations writes
RA1
DAC Coefficient RAM Write Sequence
RA[7:0]
write
Type
Type
R/W
2.5 uS
RA0
min.
EQ RAM read finished;
EQ Read Data valid
(time not fixed)
R
R
EQ RAM Write
writing 1 reigster
RD[7:0]
A
S
Default
Default
18
Lo
0
0
0
RD7
write
Write
RD[7:0]
EQ RAM
Mid
RD0
Contains the address (between 0 and 255) of the
DACCRAM to be accessed by a read or write. This is
not a byte address--it is the address of the 24-bit
data item to be accessed from the DACCRAM.This
address is automatically incremented after writing to
DACCRAM_WRITE_HI or reading from
DACCRAM_READ_HI (and the 24 bit data from the
next RAM location is fetched.)
1 = read/write to DACCRAM in progress, cleared by
HW when done.
Reserved
write
Write
RD[7:0]
EQ RAM
A
S
Hi
register write here
RD7
EQ RAM write req = 1
multiple write cycle
S
DA[6:0], W
RD0
28 SCL cycles
Description
Description
70 uS min.
write
A
RA[7:0]
S
EQ RAM Write
RD7
multiple write cycle
RD[7:0]
Lo
register write here
RD0
EQ RAM write must
have finished here;
EQ_A ++
EQ RAM Write Lo
updated here
write
A
RD[7:0]
Write
S
EQ RAM
Mid
P
ACS422X68
V1.6 01/13