ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 69

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
SDA
SCL
SCL
SDA
5.9.2.
5.9.3.
START
START
Device Address DA[6:0]
The ACS422x68 has device address D2.
Multiple Write Cycle
The controller may write more than one register within a single write cycle. To write additional regis-
ters, the controller will not generate a stop or start (repeated start) command after receiving the
acknowledge for the second byte of information (register address and data). Instead the controller
will continue to send bytes of data. After each byte of data is received, the register address is incre-
mented.
Register Read Cycle
The controller indicates the start of data transfer with a high to low transition on SDA while SCL
remains high, signalling that a device address and data will follow. If the device address received
matches the address of the ACS422x68 and the R/W bit is ‘0’, indicating a write, then the
ACS422x68 responds by pulling SDA low on the next clock pulse (ACK); otherwise, the ACS422x68
returns to the idle condition to wait for a new start condition and valid address.
Once the ACS422x68 has acknowledged a correct address, the controller sends a restart command
(high to low transition on SDA while SCL remains high). The controller then re-sends the devices
address with the R/W bit set to ‘1’ to indicate a read cycle.The ACS422x68 acknowledges by pulling
SDA low for one clock pulse. The controller then receives a byte of register data (B7 to B0).
For a single byte transfer, the host controller will not acknowledge (high on data line) the data byte
and generate a low to high transition on SDA while SCL is high, completing the transfer. If a start or
stop condition is detected out of sequence, the device returns to the idle condition.
Device Address DA[6:0]
nW
ACK
Register Address RA[7:0]
Figure 30. 2-Wire Serial Control Interface
Figure 31. Multiple Write Cycle
nW
ACK
Register Write 1
ACK
Register Address RA[7:0]
Register Data RD[7:0]
69
ACK
Register Write 2 ...
ACK
Register Data RD[7:0]
@RA[7:0]+1
Register Data RD[7:0]
ACK
Register Write n
Register Data RD[7:0]
@RA[7:0]+n
ACK
ACK
STOP
STOP
ACS422X68
V1.6 01/13