ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 79

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
8. REGISTER MAP
R10 (0Ah)
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R14 (0Eh)
R15 (0Fh)
R16 (10h)
R18 (12h)
R19 (13h)
R20 (14h)
R21 (15h)
R22 (16h)
R23 (17h)
R24 (18h)
R25 (19h)
R26 (1Ah)
R27 (1Bh)
R28 (1Ch)
R29 (1Dh)
R30 (1Eh)
R31 (1Fh)
R32 (20h)
R33 (21h)
R34 (22h)
R35 (23h)
R36 (24h)
R37 (25h)
R38 (26h)
R39 (27h)
R40 (28h)
R41 (29h)
R43 (2Bh)
R44 (2Ch)
R45 (2Dh)
R46 (2Eh)
R47 (2Fh)
R48 (30h)
R49 (31h)
R50 (32h)
R51 (33h)
R17 (11h)
R42(2Ah)
Register
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
R9 (09h)
(D15:9)
THERMSPKR1
SPKVOLR
DACVOLL
DACVOLR
ADCVOLL
ADCVOLR
CNVRTR0
CNVRTR1
THERMTS
SPKVOLL
CATKTCL
CATKTCH
CRELTCL
CRELTCH
LATKTCH
LRELTCH
CONFIG0
CONFIG1
GAINCTL
DMICCTL
COMPTH
LATKTCL
LRELTCL
HPVOLR
CMPRAT
HPVOLL
INMODE
CLECTL
MUGAIN
INVOLR
PWRM1
PWRM2
LIMTGT
INVOLL
INSELL
INSELR
ADCSR
DACSR
VUCTL
NGATE
EXPTH
LIMTH
Name
COP1
COP2
ALC0
ALC1
ALC2
ALC3
AIC1
AIC2
AIC3
CTL
Limiter Attack time constant High
Limiter Attack time constant Low
Comp release time const High
Comp release time const Low
Limiter Release time constant
Limiter Release time constant
Comp Attack time const High
Comp Attack time const Low
Speaker Thermal Algorithm
Constant Output Power1
Constant Output Power2
Volume Update Control
Compressor Threshold
Temp Sensor Control
Expander Threshold
SPKR Right volume
Right Input volume
SPKR Left volume
Right DAC volume
Right ADC volume
ADCR signal path
Compressor Ratio
ADCL signal path
ADC Sample rate
DAC Sample rate
CLEMakeUpGain
Limiter Threshold
Left DAC volume
Left ADC volume
Left Input volume
Audio Interface 1
Audio Interface 2
Audio Interface 3
Additional control
Right HP volume
ADC input mode
Left HP volume
D-Mic Control
CMPLMTCTL
Pwr Mgmt (1)
Pwr Mgmt (2)
Limiter Target
ADC Control
DAC Control
Gain Control
Noise Gate
CONFIG0
CONFIG1
Remarks
Control
ALC0
ALC1
ALC2
ALC3
High
Low
zerodet_flag
TripHighStat
CATKTC15
CRELTC15
ADCPOLR
DACPOLR
COMPTH7
LATKTC15
LRELTC15
ForcePwd
CATKTC7
CRELTC7
ADCFade
HPSWEN
COPAtten
LATKTC7
LRELTC7
LIMTGT7
EQ2_EN
EXPTH7
ASDM1
DMicEn
LIMTH7
Bit[7]
BSTL
D2S
DACDSEL[1:0]
INSEL_L[1:0]
INSEL_R[1:0]
ABCM[1:0]
DBCM[1:0]
Table 88. Register Map
TripLowStat
InstCutMod
HPSWPOL
CATKTC14
CRELTC14
COMPTH6
LATKTC14
LRELTC14
ADCPOLL
DACPOLL
CATKTC6
CRELTC6
DACFade
BCLKINV
EQ2_BE2
COPGain
HDCOMP
LATKTC6
LRELTC6
EXPTH6
ASDM0
LIMTH6
LIMTG6
MODE
BSTR
Bit[6]
IZCR
IZCL
HPL
e
DCY[3:0]
79
MAXGAIN[2:0]
MINGAIN[2:0]
zerodetlen1
CATKTC13
CRELTC13
NGTH[4:0]
COMPTH5
LATKTC13
LRELTC13
CATKTC5
CRELTC5
ADOPDD
EQ2_BE1
LATKTC5
LRELTC5
EQ2SW1
HDeltaEn
LIMTGT5
EXPTH5
DSDM1
LIMTH5
PGAL
Bit[5]
HPR
MS
AMONOMIX[1:0]
DMONOMIX[1:0]
MICBST_R[1:0]
MICBST_L[1:0]
ADCDSEL[1:0]
TripSplit[1:0]
IncRatio[1:0]
zerodetlen0
CATKTC12
CRELTC12
CLEMUG4
COMPTH4
LATKTC12
LRELTC12
CMPRAT4
CATKTC4
CRELTC4
EQ2_BE0
Lvl_Mode
LATKTC4
LRELTC4
EQ2SW0
LIMTGT4
ALRPDD
EXPTH4
INVOLU
DSDM0
LIMTH4
DMono
PGAR
Bit[4]
SPKL
LRP
DACVOL_R[7:0]
ADCVOL_R[7:0]
DACVOL_L[7:0]
ADCVOL_L[7:0]
AvgLength[3:0]
ABR[1:0]
DBR[1:0]
SPKVOL_R[6:0]
SPKVOL_L[6:0]
HPVOL_R[6:0]
HPVOL_L[6:0]
WindowSel
CATKTC11
CRELTC11
ADCVOLU
DMPhAdj1
CLEMUG3
COMPTH3
LATKTC11
LRELTC11
CMPRAT3
CRELTC3
CATKTC3
LATKTC3
LRELTC3
ABCPDD
EQ1SW1
LIMTGT3
EQ1_EN
EXPTH3
ADCMU
DACMU
LIMTH3
ADCL
SPKR
Bit[3]
TRI
TripShift[1:0]
IncStep[1:0]
INVOL_L
INVOL_R
WL[1:0]
COPTarget[4:0]
ALC MODE
CATKTC10
CRELTC10
DACVOLU
auto_mute
DMPhAdj0
CLEMUG2
COMPTH2
LATKTC10
LRELTC10
CMPRAT2
CRELTC2
DEEMPH
EQ1_BE2
CATKTC2
LATKTC2
LRELTC2
EQ1SW0
LIMTGT2
EXPTH2
DDIPDD
Exp_En
LIMTH2
HPOR
ADCR
Bit[2]
ALCL[3:0]
NGG[1:0]
HLD[3:0]
ATK[3:0]
BLRCM[2:0]
ADCHPDR
SPKVOLU
dc_bypass
CLEMUG1
COMPTH1
CMPRAT1
EQ1_BE1
CATKTC1
CATKTC9
CRELTC1
CRELTC9
LATKTC1
LRELTC1
LRELTC9
DLRPDD
ABM[2:0]
DBM[2:0]
DMRate1
LIMTGT1
LATKTC9
Limit_En
EXPTH1
LIMTH1
TSDEN
Bit[1]
MICB
FORMAT[1:0]
MonRate[1:0]
ALCSEL[1:0]
DecStep[1:0]
Poll[1:0]
sd_force_on
ADCHPDL
CLEMUG0
COMPTH0
CMPRAT0
EQ1_BE0
Comp_En
CATKTC0
CATKTC8
CRELTC0
CRELTC8
LRELTC0
LRELTC8
HPVOLU
DBCPDD
DMRate0
LIMTGT0
LATKTC0
LATKTC8
DIGENB
EXPTH0
LIMTH0
NGAT
VREF
TOEN
Bit[0]
DS
ACS422X68
V1.6 01/13
Default
BFh
BFh
C0h
A0h
77h
77h
6Fh
6Fh
FFh
FFh
17h
17h
00h
00h
00h
00h
7Bh
00h
32h
00h
0Ah
00h
00h
08h
12h
08h
12h
00h
00h
00h
09h
81h
00h
24h
08h
02h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h