ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 39

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ACS422A68TAGZBX8

Manufacturer Part Number
ACS422A68TAGZBX8
Description
Interface - CODECs
Manufacturer
IDT
Datasheet

Specifications of ACS422A68TAGZBX8

Rohs
yes
Part # Aliases
IDTACS422A68TAGZBX8
ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
Constant Output Power 3
Configuration Register
PWM Control 0 Register
R137 (89h)
Constant Output
Power 3
R31 (1Fh)
CONFIG0
R66 (42h)
PWM0
Register Address
Register Address
Register Address
5:0
7:6
5:4
3:2
7:5
Bit
Bit
Bit
7
6
1
0
5
4
3
2
1
0
quantizer_sel
DSDM[1:0]
fourthorder
ASDM[1:0]
dc_bypass
HighDelta
add3_sel
roundup
COPAdj
RSVD
RSVD
RSVD
SCTO
UVLO
Label
Label
Label
bfclr
Table 41. Constant Output Power 3 Register
Table 42. CONFIG0 Register
Table 43. PWM0 Register
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
Default
Default
Default
10h
10h
39
0h
0h
11
0
0
0
0
1
1
0
1
0
0
1 = A high delta situation has been detected (positive
code change > 4) and the constant output power
function is adjusting.
1 = Constant Output Power function will use attenuate
the BTL output if the PVDD sense circuit returns a code
higher than the target value.
Amount that the Constant Output Power function is
adjusting the signal gain. Value is 2s compliment with
each step equal to 0.1875dB. The approximate range is
+/- 6dB
ADC Modulator Rate
DAC Modulator Rate
Reserved for future use.
1 = bypass DC removal filter
(WARNING DC content can damage speakers)
Reserved
Class-D Short Circuit Detect Time-out
00 = 10uS
01 = 100uS
10 = 500uS
11 = 100mS
Under Voltage Lock Out
1 = BTL output disabled if PVDD sense circuit returns
code 0
1 = roundup, 0 = truncate for quantizer
1 = disable binomial filter
1 = 4th order binomial filter; 0 = 3rd order
1 = 24-bit Noise Shaper output (pre-quantizer)
0 = 8/9/10-bit quantizer output
Description
Description
Description
ACS422X68
V1.6 01/13

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