ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 68

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
.
The BCM mode bit clock generator produces 16, 20, or 32 bit cycles per sample.
5.9.
The registers are accessed through a serial control interface using a multi-word protocol comprised of 8-bit words. The
first 8 bits provide the device address and Read/Write flag. In a write cycle, the next 8 bits provide the register address;
all subsequent words contain the data, corresponding to the 8 bits in each control register.The control interface oper-
ates using a standard 2-wire interface, as a slave device only.
LRCLK
Fs x 64
Fs x 40
Fs x 32
R23/R25 (17h/19h
ADC/DAC Sample
Rate Control
Register Address
Control Interface
5.9.1.
Register Write Cycle
The controller indicates the start of data transfer with a high to low transition on SDA while SCL
remains high, signalling that a device address and data will follow. All devices on the 2-wire bus
respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit,
MSB first). If the device address received matches the address of the ACS422x68 and the R/W bit is
‘0’, indicating a write, then the ACS422x68 responds by pulling SDA low on the next clock pulse
(ACK); otherwise, the ACS422x68 returns to the idle condition to wait for a new start condition and
valid address.
Once the ACS422x68 has acknowledged a correct device address, the controller sends the
ACS422x68 register address. The ACS422x68 acknowledges the register address by pulling SDA
low for one clock pulse (ACK). The controller then sends a byte of data (B7 to B0), and the
ACS422x68 acknowledges again by pulling SDA low.
When there is a low to high transition on SDA while SCL is high, the transfer is complete. After
receiving a complete address and data sequence the ACS422x68 returns to the idle state. If a start
or stop condition is detected out of sequence, the device returns to the idle condition.
Note: The clock cycles are evenly distributed throughout the frame (true multiple of LRCLK not a
gated clock.)
Bit
7:6
Table 74. Master Mode BCLK Frequency Control Register
ABCM[1:0]
DBCM[1:0]
Label
Figure 29. Bit Clock mode
Type
RW
Default
68
00
BCLK Frequency
00 = Auto
01 = 32 x fs
10 = 40 x fs
11 = 64 x fs
Description
ACS422X68
V1.6 01/13