ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 73

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
6.3.
The power consumption and audio quality may be adjusted by changing the converter modulator rate. By default the
R25 (19h)
DAC Sample Rate
Control
(DACSR)
Register Address
DAC/ADC Modulator Rate Control
The clocking of the ACS422x68 is controlled using the BR[1:0] and BM[2:0] control bits. Each value
of BR[1:0] + BM[2:0]selects one combination of ACLK division ratios and hence one combination of
sample rates
The BR[1:0] and BM[2:0] bits must be set to configure the appropriate ADC and DAC sample rates in
both master and slave mode.
BR [1:0]
Bit
7:6
4:3
2:0
5
00
01
10
11
DBCM[1:0]
DBM[2:0]
DBR[1:0]
RSVD
Label
BM [2:0]
100-111
100-111
100-111
000-111
000
001
010
000
001
010
000
001
010
011
011
011
Table 81. ACLK and Sample Rates
Table 80. DACSR Register
Type
RW
RW
RW
R
56.448
40.96
61.44
ACLK
-
Default
73
MHz
MHz
MHz
010
00
10
0
DAC Bit Clock Mode (for data interface DACBCLK
generation in master mode)
00 = Auto
01 = 32x fs
10 = 40x fs
11 = 64x fs
Reserved
DAC Base Rate
00 = 32KHz
01 = 44.1KHz
10 = 48KHz
11 = Reserved
DAC Base Rate Multiplier
000 = 0.25x
001 = 0.50x
010 = 1x
011 = 2x
100-111 = Reserved
11.025 kHz (MCLK/5120)
22.05 kHz (MCLK/2560)
44.1 kHz (MCLK/1280)
88.2 kHz (MCLK/640)
16 kHz (MCLK/2560)
32 kHz (MCLK/1280)
12 kHz (MCLK/5120)
24 kHz (MCLK/2560)
48 kHz (MCLK/1280)
8 kHz (MCLK/5120)
96 kHz (MCLK/640)
SAMPLE RATE
Reserved
Reserved
Reserved
Reserved
Reserved
Description
ACS422X68
V1.6 01/13