ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 19

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
•
DACCRAM EQ Addresess
SCL
SDA
EQ RAM read operation
Addr
0x00
0x01
0x02
Generic read operation
1. DA: Device Address
2. RA: Register Address
3. EQ_A: EQ RAM Address
4. RD: Register Data
5. A
S
: Acknowledge from slave
S
RA7
DA[6:0], W
EQ_COEF_0F0_B0
EQ_COEF_0F0_B1
EQ_COEF_0F0_B2
RA1
Coefficients
Channel 0
RA[7:0]
write
RA0
Reading back a value from the DACCRAM is done in this manner:
1. Write target address to DACCRAM_ADDR register.(EQ data is pre-fetched for read even if we
2. Start (or repeat start) a write cycle to DACCRAM_READ_LO and after the second byte (register
3. Signal a repeat start and indicate a read operation
4. Read D7:0 (register address incremented after ack by host)
5. Read D15:8 (register address incremented after ack by host)
6. Read D23:16 (register address incremented and next EQ location pre-fetched after ack by host)
7. The host stops the bus cycle
To repeat a read cycle for consecutive EQ RAM locations:
1. Start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating
2. After the second byte is acknowledged, signal a repeated start.
3. Indicate a read operation
4. Read the DACCRAM_READ_LO register as described in step 4
5. Read the DACCRAM_READ_MID register as described in step 5
6. Read the DACCRAM_READ_HI register as described in step 6
7. Repeat steps 8-13 as desired
EQ RAM Address
10. P: Stop
7. N
8. S: Start
6. A
9. S
don’t use it)
address) is acknowledged, go to step 3. (Do not complete the write cycle.)
DACCRAM_RD_LO as the target address.
A
M
M
r
: Repeated Start
: Not Acknowledge from master
S
RD[7:0]
: Acknowledge from master
EQ 0
EQ_A updated;
EQ RAM read req = 1
S
r
P
S
Addr
0x20
0x21
0x22
DA[6:0], W
DA6
read 1 register
Figure 7. DAC Coefficient RAM Read Sequence
DA0
30 SCL cycles
EQ_COEF_1F0_B0
EQ_COEF_1F0_B1
EQ_COEF_1F0_B2
75 uS min.
repeat for multiple consecutive EQ RAM locations reads
write
RAM Read
Lo,
RA[7:0]
Coefficients
truncate
Channel 1
EQ
R
S
r
A
DA[6:0], R
S
RD7
EQ RAM Data
must be valid here
read
19
Data
RD[7:0]
EQ RAM
RD0
Addr
0x40
0x41
0x42
Lo
read
A
Data
M
RD[7:0]
EQ RAM
EQ_COEF_2F0_B0
EQ_COEF_2F0_B1
EQ_COEF_2F0_B2
Mid
RD7
multiple read cycle
Coefficients
Channel 0
read
Data
RD[7:0]
EQ RAM
RD0
Hi
NACK from master to end read cycle
P
EQ_A ++; prefetch data
A
S
M
DA[6:0], W
EQ1
RD7
multiple read cycle
Addr
0x60
0x61
0x62
write
RAM Read
Lo,
RD0
RA[7:0]
truncate
EQ
EQ_COEF_3F0_B0
EQ_COEF_3F0_B1
EQ_COEF_3F0_B2
N
M
S
r
DA[6:0], R
Coefficients
Channel 1
EQ RAM Data
must be valid here
read
Data
RD[7:0]
EQ RAM
ACS422X68
V1.6 01/13
Lo