DS3172 Maxim Integrated, DS3172 Datasheet - Page 112
DS3172
Manufacturer Part Number
DS3172
Description
Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
Manufacturer
Maxim Integrated
Datasheet
1.DS3171.pdf
(234 pages)
Specifications of DS3172
Part # Aliases
90-31720-000
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10.12.3 Detailed Description
The receiver performs clock and data recovery from an alternate mark inversion (AMI) coded signal or a B3ZS- or
HDB3-coded AMI signal and monitors for loss of the incoming signal. The transmitter drives standard pulse-shape
waveforms onto 75Ω coaxial cable. See
The jitter attenuator can be mapped into the receiver data path, mapped into the transmitter data path, or be
disabled. The DS3/E3 LIU conforms to the telecommunications standards listed in
external components required for proper operation.
Figure 10-32. DS3/E3 LIU Block Diagram
10.12.4 Transmitter
10.12.4.1 Transmit Clock
The clock used in the LIU Transmitter is typically based on either the CLAD clock or TCLKI, selected by the
CLADC bit in PORT.CR3.
10.12.4.2 Waveshaping, Line Build-Out, Line Driver
The waveshaping block converts the transmit clock, positive data, and negative data signals into a single AMI
signal with the waveshape required for interfacing to DS3/E3 lines.
(AC Timing section) show the waveform template specifications and test parameters.
Because DS3 signals must meet the waveform templates at the cross-connect through any cable length from 0 to
450ft, the waveshaping circuitry includes a selectable LBO feature. For cable lengths of 225ft or greater, the TLBO
configuration bit (PORT.CR2.TLBO) should be low. When TLBO is low, output pulses are driven onto the coaxial
cable without any preattenuation. For cable lengths less than 225ft, TLBO should be high to enable the LBO
circuitry. When TLBO is high, pulses are preattenuated by the LBO circuitry before being driven onto the coaxial
cable. The LBO circuitry provides attenuation that mimics the attenuation of 225ft of coaxial cable.
FROM DS3/E3
TO DS3/E3 LINE
LINE
TXPn
TXNn
RXPn
RXNn
VDD
VSS
Supply
Power
Analog
Local
Loopback
Monitor
Driver
CLKA
Automatic
Equalizer
Adaptive
Control
Clock Rate
Gain
Adapter
+
ALOS
CLKB
Figure 10-32
squelch
CLKC
Recovery
Clock &
Data
for a detailed functional block diagram of the DS3/E3 LIU.
112
Table 18-6
TO B3ZS/HDB3
FROM B3ZS/HDB3
through
DECODER
ENCODER
Table
Table 18-8
4-1.
Figure 1-1
and
Figure 18-9
shows the
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