DS3172 Maxim Integrated, DS3172 Datasheet - Page 34

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

PIN NAME
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
JTCLK
JTRST
JTMS
JTDO
TEST
JTDI
RST
HIZ
TYPE
Ipu
Ipu
Ipu
Oz
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
General-Purpose IO 1
GPIO1: This signal is configured to be a general-purpose IO pin, or an alarm output signal for
port 1.
General-Purpose IO 2
GPIO2: This signal is configured to be a general-purpose IO pin, or the 8KREFO output signal,
or an alarm output signal for port 1.
General-Purpose IO 3
GPIO3: This signal is configured to be a general-purpose IO pin, or an alarm output signal for
port 2.
General-Purpose IO 4
GPIO4: This signal is configured to be a general-purpose IO pin, or the 8KREFI input signal, or
an alarm output signal for port 2. When configured for 8KREFI mode the signal frequency
should be 8,000 Hz +/- 500 ppm and about 50% duty cycle.
General-Purpose IO 5
GPIO5: This signal is configured to be a general-purpose IO pin, or an alarm output signal for
port 3.
General-Purpose IO 6
GPIO6: This signal is configured to be a general-purpose IO pin, or the TMEI input signal, or an
alarm output signal for port 3. When configured for TMEI input, the signal low time and high
time must be greater than 500 ns.
General-Purpose IO 7
GPIO7: This signal is configured to be a general-purpose IO pin, or an alarm output signal for
port 4.
General-Purpose IO 8
GPIO8: This signal is configured to be a general-purpose IO pin, or the PMU input signal, or an
alarm output signal for port 4. When configured for PMU input, the signal low time and high time
must be greater than 500 ns.
Test enable (active low)
TEST: This signal enables the internal scan test mode when low. For normal operation tie high.
This is an asynchronous input.
High impedance test enable (active low)
HIZ: This signal puts all digital output and bi-directional pins in the high impedance state when
it low and JTRST is low. For normal operation tie high. This is an asynchronous input.
Reset (active low)
RST: This signal resets all the internal processor registers and logic when low. This pin should
be low while power is applied and set high after the power is stable. This is an asynchronous
input.
JTAG Clock
JTCLK: This clock input is typically a low frequency (less than 10 MHz) 50% duty cycle clock
signal.
JTAG Mode Select (with pull-up)
JTMS: This input signal is used to control the JTAG controller state machine and is sampled on
the rising edge of JTCLK.
JTAG Data Input (with pull-up)
JTDI: This input signal is used to input data into the register that is enabled by the JTAG
controller state machine and is sampled on the rising edge of JTCLK.
JTAG Data Output
JTDO: This output signal is the output of an internal scan shift register enabled by the JTAG
controller state machine and is updated on the falling edge of JTCLK. The pin is in the high
impedance mode when a register is not selected or when the JTRST signal is high. The pin
goes into and exits the high impedance mode after the falling edge of JTCLK
JTAG Reset (active low with pullup)
JTRST: This input forces the JTAG controller logic into the reset state and forces the JTDO pin
into high impedance when low. This pin should be low while power is applied and set high after
the power is stable. The pin can be driven high or low for normal operation, but must be high for
JTAG operation.
MISC I/O
JTAG
34
PIN DESCRIPTION