DS3172 Maxim Integrated, DS3172 Datasheet - Page 9

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

DS3171/DS3172/DS3173/DS3174
Figure 10-20. HDLC Controller Block Diagram ......................................................................................................... 96
Figure 10-21. Trail Trace Controller Block Diagram .................................................................................................. 99
Figure 10-22. Trail Trace Byte (DT = Trail Trace Data)........................................................................................... 101
Figure 10-23. FEAC Controller Block Diagram........................................................................................................ 102
Figure 10-24. FEAC Codeword Format................................................................................................................... 103
Figure 10-25. Line Encoder/Decoder Block Diagram .............................................................................................. 104
Figure 10-26. B3ZS Signatures ............................................................................................................................... 106
Figure 10-27. HDB3 Signatures............................................................................................................................... 106
Figure 10-28. BERT Block Diagram ........................................................................................................................ 107
Figure 10-29. PRBS Synchronization State Diagram.............................................................................................. 109
Figure 10-30. Repetitive Pattern Synchronization State Diagram........................................................................... 110
Figure 10-31. LIU Functional Diagram..................................................................................................................... 111
Figure 10-32. DS3/E3 LIU Block Diagram............................................................................................................... 112
Figure 10-33. Receiver Jitter Tolerance .................................................................................................................. 115
Figure 13-1. JTAG Block Diagram........................................................................................................................... 210
Figure 13-2. JTAG TAP Controller State Machine .................................................................................................. 211
Figure 13-3. JTAG Functional Timing...................................................................................................................... 214
Figure 14-1. DS3174 Pin Assignments—400-Lead PBGA ..................................................................................... 215
Figure 14-2. DS3173 Pin Assignments—400-Lead PBGA ..................................................................................... 216
Figure 14-3. DS3172 Pin Assignments—400-Lead PBGA ..................................................................................... 216
Figure 14-4. DS3171 Pin Assignments—400-Lead PBGA ..................................................................................... 217
Figure 18-1. Clock Period and Duty Cycle Definitions............................................................................................. 222
Figure 18-2. Rise Time, Fall Time, and Jitter Definitions......................................................................................... 222
Figure 18-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) .................................................................... 222
Figure 18-4. Hold, Setup, and Delay Definitions (Falling Clock Edge).................................................................... 223
Figure 18-5. To/From Hi Z Delay Definitions (Rising Clock Edge) .......................................................................... 223
Figure 18-6. To/From Hi Z Delay Definitions (Falling Clock Edge) ......................................................................... 223
Figure 18-7. Micro Interface Nonmultiplexed Read/Write Cycle ............................................................................. 227
Figure 18-8. Micro Interface Multiplexed Read Cycle.............................................................................................. 228
Figure 18-9. E3 Waveform Template....................................................................................................................... 230
Figure 18-10. DS3 Pulse Mask Template................................................................................................................ 231
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