DS3172 Maxim Integrated, DS3172 Datasheet - Page 162

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 2: Receive FIFO Full (RFF) – When 0, the Receive FIFO contains 255 or less bytes of data. When 1, the
Receive FIFO is full.
Bit 1: Receive FIFO Empty (RFE) – When 0, the Receive FIFO contains at least one byte of data. When 1, the
Receive FIFO is empty.
Bit 0: Receive HDLC Data Available (RHDA) – When 0, the Receive FIFO contains less data than the Receive
HDLC data available level (RDAL[4:0]). When 1, the Receive FIFO contains the same or more data than the
Receive HDLC data available level.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 7: Receive FIFO Overflow Latched (RFOL) – This bit is set when a Receive FIFO overflow condition occurs.
An overflow condition results in a loss of data.
Bit 4: Receive Packet End Latched (RPEL) – This bit is set when an end of packet is stored in the Receive FIFO.
Bit 3: Receive Packet Start Latched (RPSL) – This bit is set when a start of packet is stored in the Receive FIFO.
Bit 2: Receive FIFO Full Latched (RFFL) – This bit is set when the RFF bit transitions from 0 to 1.
Bit 0: Receive HDLC Data Available Latched (RHDAL) – This bit is set when the RHDA bit transitions from 0 to
1.
RFOL
15
15
--
--
--
7
7
14
14
--
--
--
--
6
6
HDLC.RSR
HDLC Receive Status Register
(0,2,4,6)B4h
HDLC.RSRL
HDLC Receive Status Register Latched
(0,2,4,6)B6h
13
13
--
--
--
--
5
5
RPEL
12
12
--
--
--
4
4
162
RPSL
11
11
--
--
--
3
3
RFFL
RFF
10
10
--
--
2
2
RFE
--
--
--
9
1
9
1
RHDAL
RHDA
--
--
8
0
8
0