DS3172 Maxim Integrated, DS3172 Datasheet - Page 57

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

10.2.3 Line IO Pin Timing Source Selection
The line IO pins can use any input clock pin (RLCLKn or TCLKIn) or output clock pin (TLCLKn, RCLKOn, or
TCLKOn) for its clock pin and meet the AC timing specifications as long as the clock signal is valid for the mode the
part is in. The clock select bit for the transmit line IO signal group PORT.CR3.TLTS selects the correct input or
output clock timing.
10.2.3.1 Transmit Line Interface Pins Timing Source Selection
(TPOSn/TDATn, TNEGn)
The transmit line interface signal pin group has the same functional timing clock source as the TLCLKn pin
described in
output pin is always a valid output clock for external logic to use for these signals when PORT.CR3.TLTS=0.
The transmit line timing select bit (TLTS) is used to select input or output clock pin timing. When TLTS=0, output
clock timing is selected. When TLTS=1, input clock timing is selected. If TLTS is set for input clock timing and an
output clock pin is used, or if TLTS is set for output clock timing and an input clock pin is used, then the setup, hold
and delay timings, as specified in Section
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the RX LIU or the CLAD.
Table 10-6. Transmit Line Interface Signal Pin Valid Timing Source Select
10.2.3.2 Transmit Framer Pin Timing Source Selection
(TSERn, TSOFIn, TSOFOn/TDENn)
The transmit framer signal pin group has the same functional timing clock source as the TCLKO pin described in
Table
valid output clock for external logic to use for these signals when TFTS=0.
The transmit framer select bit (TFTS) is used to select input or output clock pin timing. When TFTS=0, output clock
timing is selected. When TFTS=1, input clock timing is selected. If TFTS is set for input clock timing and an output
clock pin is used, or If TFTS is set for output clock timing and an input clock pin is used, then the setup, hold and
delay timings, as specified in Section
modes in which there is no input clock pin available for external timing since the clock source is derived internally
from the RX LIU or the CLAD.
1
1
1
0
0
0
0
0
0
0
0
10-4. Other clock pins can be used for the external timing. The TCLKO transmit clock output pin is always a
not LLB (010) and not PLB (011)
not LLB (010) and not PLB (011)
not LLB (010), not PLB (011)
Table
and not LLB&DLB (110)
and not LLB&DLB (110)
and not LLB&DLB (110)
LLB (010) or PLB (011)
LLB (010) or PLB (011)
LLB (010) or PLB (011)
or DLB&LLB (110)
or DLB&LLB (110)
DLB&LLB (110)
not DLB (100),
10-3. Other clock pins can be used for the external timing. The TLCLKn transmit line clock
DLB (100)
LBM[2:0]
XXX
XXX
XXX
18.1
18.1
will not be valid. There are some combinations of TFTS=1 and other
will not be valid. There are some combinations of TLTS=1 and other
X
X
X
X
X
X
X
0
1
0
1
X
X
X
X
X
X
X
X
X
0
1
57
0
1
1
0
0
0
0
1
1
1
1
Valid Timing to These Clock Pins
TLCLKn, TCLKOn, RCLKOn
TLCLKn, RCLKOn
No valid timing to any input clock pin
TCLKIn
No valid timing to any input clock pin
TLCLKn, TCLKOn, RCLKOn
RLCLKn
No valid timing to any input clock pin
TLCLKn
TLCLKn, TCLKOn (default)
RLCLKn