DS3172 Maxim Integrated, DS3172 Datasheet - Page 167

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Transmit FEAC Idle Interrupt Enable (TFIIE) – This bit enables an interrupt if the TFIL bit is set and the bit
in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
12.7.2 FEAC Receive Side Register Map
The receive side utilizes five registers.
Table 12-20. FEAC Receive Side Register Map
12.7.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 0: Receive FEAC Reset (RFR) –When 0, the Receive FEAC Processor and Receive FEAC FIFO will resume
normal operations. When 1, the Receive FEAC controller is reset. The FEAC FIFO is emptied, any transfer in
progress is halted, and all incoming data is discarded.
(0,2,4,6)D0h FEAC.RCR
(0,2,4,6)D2h
(0,2,4,6)D4h FEAC.RSR
(0,2,4,6)D6h FEAC.RSRL
(0,2,4,6)D8h FEAC.RSRIE
(0,2,4,6)DAh
(0,2,4,6)DCh FEAC.RFDR
(0,2,4,6)DEh
Address
0 = interrupt disabled
1 = interrupt enabled
15
15
--
--
--
--
0
7
0
0
7
0
Register
--
--
--
14
14
--
--
--
--
0
6
0
0
6
0
FEAC.TSRIE
FEAC Transmit Status Register Interrupt Enable
(0,2,4,6)C8h
FEAC.RCR
FEAC Receive Control Register
(0,2,4,6)D0h
FEAC Receive Control Register
Unused
FEAC Receive Status Register
FEAC Receive Status Register Latched
FEAC Receive Status Register Interrupt Enable
Unused
FEAC Receive FIFO Data Register
Unused
Register Description
13
13
--
--
--
--
0
5
0
0
5
0
12
12
--
--
0
0
--
0
--
0
4
4
167
11
11
--
--
--
--
0
3
0
1
3
0
10
10
--
--
--
--
0
2
0
0
2
0
--
--
--
--
9
0
1
0
9
0
1
0
TFIIE
RFR
--
--
8
0
0
0
8
0
0
0