DS3172 Maxim Integrated, DS3172 Datasheet - Page 208

• Manufacturer Part Number: DS3172
• Description: Network Controller & Processor ICs Dual DS3/E3 Single Chip Transceiver
• Manufacturer: Maxim Integrated

Specifications of DS3172

• Part # Aliases: 90-31720-000

12.9.8 Receive Clear Channel
The receive Clear Channel mode utilizes four registers.
12.9.8.1 Register Map
Table 12-30. Receive Clear Channel Register Map
12.9.8.2 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS condition will cause
downstream AIS to be inserted. When 1, the presence of an LOS condition will not cause downstream AIS to be
inserted.
(1,3,5,7)2Ah
(1,3,5,7)2Ch
(1,3,5,7)2Eh
(1,3,5,7)3Ah
(1,3,5,7)3Ch
(1,3,5,7)3Eh
(1,3,5,7)20h
(1,3,5,7)22h
(1,3,5,7)24h
(1,3,5,7)26h
(1,3,5,7)28h
(1,3,5,7)30h
(1,3,5,7)32h
(1,3,5,7)34h
(1,3,5,7)36h
(1,3,5,7)38h
Address
Reserved
Reserved
15
0
7
0
CC.RSRIE1
CC.RSRL1
CC.RSR1
Register
CC.RCR
Reserved
Reserved
--
--
--
--
--
--
--
--
--
--
--
--
14
0
6
0
CC.RCR
Clear Channel Receive Control Register
(1,3,5,7)20h
Clear Channel Receive Control Register
Reserved
Clear Channel Receive Status Register #1
Reserved
Clear Channel Receive Status Register Latched #1
Reserved
Clear Channel Receive Status Register Interrupt Enable #1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Unused
Unused
Reserved
Reserved
Register Description
13
0
5
0
Reserved
MDAISI
12
0
0
4
208
Reserved
AAISD
11
0
3
0
Reserved
Reserved
10
0
2
0
Reserved
Reserved
9
0
1
0
Reserved
Reserved
8
0
0
0