C8051F587-IMR Silicon Labs, C8051F587-IMR Datasheet - Page 204
C8051F587-IMR
Manufacturer Part Number
C8051F587-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 96 kB 8 kB SPI 2xUART
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F587-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051F58x/F59x
SFR Definition 20.16. P0SKIP: Port 0 Skip
SFR Address = 0xD4; SFR Page = 0x0F
SFR Definition 20.17. P1: Port 1
SFR Address = 0x90; SFR Page = All Pages; Bit-Addressable
204
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
P0SKIP[7:0]
P1[7:0]
Name
Name
7
0
7
1
Port 1 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 0 Crossbar Skip Enable Bits.
These bits select Port 0 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
6
0
6
1
Description
5
0
5
1
Rev. 1.2
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P0SKIP[7:0]
P1[7:0]
R/W
R/W
Function
Write
3
0
3
1
2
0
2
1
0: P1.n Port pin is logic
LOW.
1: P1.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
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