C8051F587-IMR Silicon Labs, C8051F587-IMR Datasheet - Page 225
C8051F587-IMR
Manufacturer Part Number
C8051F587-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 96 kB 8 kB SPI 2xUART
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F587-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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LIN Register Definition 21.7. LIN0ERR: LIN0 Error Register
Indirect Address = 0x0A
Name
Reset
Bit
7:5
Type
4
3
2
1
0
Bit
BITERR
SYNCH
Unused
Name
PRTY
TOUT
CHK
R
7
0
Read = 000b; Write = Don’t Care
Synchronization Error Bit (slave mode only).
0: No error with the SYNCH FIELD has been detected.
1: Edges of the SYNCH FIELD are outside of the maximum tolerance.
Parity Error Bit (slave mode only).
0: No parity error has been detected.
1: A parity error has been detected.
Timeout Error Bit.
0: A timeout error has not been detected.
1: A timeout error has been detected. This error is detected whenever one of the fol-
lowing conditions is met:
•
•
•
•
Checksum Error Bit.
0: Checksum error has not been detected.
1: Checksum error has been detected.
Bit Transmission Error Bit.
0: No error in transmission has been detected.
1: The bit value monitored during transmission is different than the bit value sent.
R
6
0
The master is expecting data from a slave and the slave does not respond.
The slave is expecting data but no data is transmitted on the bus.
A frame is not finished within the maximum frame length.
The application does not set the DTACK bit (LIN0CTRL.4) or STOP bit
(LIN0CTRL.7) until the end of the reception of the first byte after the identifier.
R
5
0
SYNCH
Rev. 1.2
R
4
0
Function
PRTY
R
3
0
C8051F58x/F59x
TOUT
R
2
0
CHK
R
1
0
BITERR
R
0
0
225
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