C8051F587-IMR Silicon Labs, C8051F587-IMR Datasheet - Page 270
C8051F587-IMR
Manufacturer Part Number
C8051F587-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 96 kB 8 kB SPI 2xUART
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F587-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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C8051F58x/F59x
26. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
270
SYSCLK
Clock Divide
SPI0CKR
SFR Bus
SPI0DAT
Logic
Write
Transmit Data Buffer
Receive Data Buffer
7
6
Figure 26.1. SPI Block Diagram
Shift Register
5
SPI CONTROL LOGIC
4
3
Data Path
2
SFR Bus
Control
SPI0CFG
SPI0DAT
1
SPI0DAT
Read
0
Rev. 1.2
Tx Data
Rx Data
Pin Interface
Control
Control
Logic
Pin
SPI0CN
MOSI
MISO
SCK
NSS
O
C
R
S
S
B
A
R
SPI IRQ
Port I/O
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