C8051F587-IMR Silicon Labs, C8051F587-IMR Datasheet - Page 37
![no-image](/images/no-image-200.jpg)
C8051F587-IMR
Manufacturer Part Number
C8051F587-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 96 kB 8 kB SPI 2xUART
Manufacturer
Silicon Labs
Datasheet
1.C8051F585-IQR.pdf
(356 pages)
Specifications of C8051F587-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
- Current page: 37 of 356
- Download datasheet (3Mb)
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground pad.
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Dimension
calculated based on a Fabrication Allowance of 0.05 mm.
metal pad is to be 60 m minimum, all the way around the pad.
good solder paste release.
Components.
C1
C2
X1
e
Table 4.6. QFN-40 Landing Diagram Dimensions
5.80
5.80
0.15
Min
Figure 4.6. QFN-40 Landing Diagram
0.50 BSC
Max
5.90
5.90
0.25
Rev. 1.2
Dimension
X2
Y1
Y2
C8051F58x/F59x
4.10
0.75
4.10
Min
Max
4.20
0.85
4.20
37
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