MT48H8M16LFB4-8 TR Micron Technology Inc, MT48H8M16LFB4-8 TR Datasheet - Page 25

• Manufacturer Part Number: MT48H8M16LFB4-8 TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1052-2

WRITEs
Figure 16: WRITE Command
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command, pro-
vided that auto precharge was not activated. The BURST TERMINATE command should
be issued x cycles before the clock edge at which the last desired data element is valid,
where x equals the CAS latency minus one. This is shown in Figure 15 for each possible
CAS latency; data element n + 3 is the last desired data element of a longer burst.
WRITE bursts are initiated with a WRITE command, as shown in Figure 16.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other com-
mands have been initiated, the DQ will remain High-Z and any additional input data will
be ignored (see Figure 18 on page 26). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to column 0 and continue.)
A9, A11
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 19 on page 27. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The 128Mb SDRAM uses a pipe-
lined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
A0-A8
BA0,1
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
HIGH
VALID ADDRESS
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
DON’T CARE
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
READs