MT48H8M16LFB4-8 TR Micron Technology Inc, MT48H8M16LFB4-8 TR Datasheet - Page 33

• Manufacturer Part Number: MT48H8M16LFB4-8 TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1052-2

WRITE with Auto Precharge
Figure 29: WRITE With Auto Precharge Interrupted by a READ
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Note:
Note:
3. Interrupted by a READ (with or without auto precharge): When a READ to bank m reg-
4. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
Internal
States
Internal
States
isters, it will interrupt a WRITE on bank n, with the data-out appearing 2 or 3 clocks
later, (depending on CAS latency). The precharge to bank n will begin after
met, where
to bank n will be data-in registered one clock prior to the READ to bank m (Figure 29).
registers, it will interrupt a WRITE on bank n. The precharge to bank n will begin after
t
data WRITE to bank n will be data registered one clock prior to a WRITE to bank m
(Figure 30).
WR is met, where
DQM is LOW.
DQM is LOW.
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
CLK
DQ
CLK
DQ
t
WR begins when the READ to bank m is registered. The last valid WRITE
Page Active
T0
NOP
Page Active
T0
NOP
t
WR begins when the WRITE to bank m is registered. The last valid
WRITE - AP
BANK n,
Page Active
BANK n
COL a
WRITE - AP
T1
D
BANK n,
a
Page Active
IN
BANK n
COL a
T1
D
WRITE with Burst of 4
a
IN
WRITE with Burst of 4
33
a + 1
T2
D
NOP
IN
T2
a + 1
D
NOP
IN
BANK m,
READ - AP
T3
COL d
BANK m
Interrupt Burst, Write-Back
t
T3
a + 2
CL = 3 (BANK m)
WR - BANK n
READ with Burst of 4
D
NOP
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
NOP
BANK m,
WRITE - AP
COL d
BANK m
T4
D
t
d
IN
Interrupt Burst, Write-Back
WR - BANK n
WRITE with Burst of 4
T5
NOP
Precharge
t
RP - BANK n
T5
d + 1
NOP
D
128Mb: x16 Mobile SDRAM
IN
T6
D
NOP
OUT
d
DON’T CARE
T6
d + 2
NOP
D
t RP - BANK n
IN
Precharge
T7
©2003 Micron Technology, Inc. All rights reserved.
D
d + 1
NOP
OUT
t RP - BANK m
DON’T CARE
T7
d + 3
NOP
D
t WR - BANK m
IN
Write-Back
Power-Down
t
WR is