MT48H8M16LFB4-8 TR Micron Technology Inc, MT48H8M16LFB4-8 TR Datasheet - Page 5

• Manufacturer Part Number: MT48H8M16LFB4-8 TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1052-2

Figure 2: Part Numbering Diagram
General Description
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
The Micron
containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 32,554,432-bit banks is organized as 4,096 rows by 512 columns
by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless high-speed, random-access opera-
tion.
The 128Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, deep power-down mode. All inputs
and outputs are LVTTL-compatible.
54-ball VFBGA (8mm x 8mm)
54-ball VFBGA (8mm x 8mm) Lead-Free
V
1.8/1.8V
DD
/V
DD
Q
MT48
Example Part Number: MT48H8M16LFF4-8 IT
Configuration
®
8 Meg x16
128Mb SDRAM is a high-speed CMOS, dynamic random-access memory
Package
V
V
DD
DD
H
Q
/
Configuration
8M16LF
5
B4
F4
Package
Micron Technology, Inc., reserves the right to change products or specifications without notice.
–
-10
Speed
-8
None
IT
Speed Grade
Operating Temp
8ns
9.6ns
128Mb: x16 Mobile SDRAM
Extended
Industrial
Temp
General Description
©2003 Micron Technology, Inc. All rights reserved.