MT48H8M16LFB4-8 TR Micron Technology Inc, MT48H8M16LFB4-8 TR Datasheet - Page 37

• Manufacturer Part Number: MT48H8M16LFB4-8 TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1052-2

Table 9:
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Current State
Precharging
(With Auto
(With Auto
Activating,
Precharge)
Precharge)
Precharge
Precharge
Active, or
Disabled)
Disabled)
(Auto
Write
(Auto
Write
Read
Read
Row
Any
Idle
Truth Table 4 – Current State Bank n, Command to Bank m
Notes: 1-6; notes appear below and on next page.
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes: 1. This table applies when CKE
RAS#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
2. This table describes alternate bank operation, except where noted; i.e., the current state is
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
6. All states and sequences not shown are illegal or reserved.
t
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
Idle:
Row Active: A row in the bank has been activated, and
Read:
Write:
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto
Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto
when all banks are idle.
represented by the current state only.
XSR has been met (if the previous state was self refresh).
CAS#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
WE#
The bank has been precharged, and
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has not
yet terminated or been terminated.
precharge enabled, and ends when
bank will be in the idle state.
precharge enabled, and ends when
bank will be in the idle state.
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any command allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
37
n-1
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
t
RP has been met. Once
RP has been met. Once
n
RP has been met.
is HIGH (see Truth Table 2) and after
128Mb: x16 Mobile SDRAM
t
RCD has been met. No data
©2003 Micron Technology, Inc. All rights reserved.
Power-Down
t
t
RP is met, the
RP is met, the
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
Notes
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9