MT48H8M16LFB4-8 TR Micron Technology Inc, MT48H8M16LFB4-8 TR Datasheet - Page 30

• Manufacturer Part Number: MT48H8M16LFB4-8 TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1052-2

Figure 24: PRECHARGE Command
Deep Power-Down
CLOCK SUSPEND
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
A0–A9, A11
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data on the memory array will not
be retained once deep power-down mode is executed. Deep power-down mode is
entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH
at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep
power-down.
In order to exit deep power-down mode, CKE must be asserted HIGH. After exiting, the
following sequence is needed in order to enter a new command. Maintain NOP input
conditions for a minimum of 100µs. Issue PRECHARGE commands for all banks. Issue
eight or more AUTO REFRESH commands. The values of the mode register and
extended mode register will be retained upon exiting deep power-down.
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 25, and Figure 26 on page 31.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
BA0,1
RAS#
CAS#
WE#
CLK
CKE
A10
CS#
HIGH
VALID ADDRESS
Bank Selected
All Banks
ADDRESS
BANK
DON’T CARE
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Power-Down