MT48H8M16LFB4-8 TR Micron Technology Inc, MT48H8M16LFB4-8 TR Datasheet - Page 28

• Manufacturer Part Number: MT48H8M16LFB4-8 TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1052-2

Figure 21: WRITE-To-PRECHARGE
PRECHARGE
Power-Down
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Note:
t
The PRECHARGE command (see Figure 24 on page 30) is used to deactivate the open
row in a particular bank or the open row in all banks. The bank(s) will be available for a
subsequent row access some specified time (
issued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (64ms) since no refresh operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
COMMAND
t
WR @
WR @
ADDRESS
ADDRESS
DQM
DQM
t
CLK
t
CK < 15ns
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
DQ
DQ
CK 15ns
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
n + 1
n + 1
NOP
NOP
T1
D
D
IN
IN
t
WR
PRECHARGE
(a or all)
BANK
T2
NOP
t
WR
PRECHARGE
(a or all)
BANK
T3
NOP
t RP
28
NOP
NOP
T4
t RP
BANK a,
ACTIVE
ROW
NOP
T5
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK a,
ACTIVE
ROW
t
T6
NOP
CKS). See Figure 22 on page 29.
t
RP) after the precharge command is
128Mb: x16 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Power-Down