DS1874T+ Maxim Integrated Products, DS1874T+ Datasheet - Page 21

• Manufacturer Part Number: DS1874T+
• Description: IC CTLR SFP+ ANLG LDD 28-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controllerr

Specifications of DS1874T+

• Number Of Channels: 1
• Voltage - Supply: 2.85 V ~ 3.9 V
• Current - Supply: 2.5mA
• Operating Temperature: -40°C ~ 95°C
• Package / Case: 28-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Number Of Outputs: 5
• Duty Cycle (max): 50 %
• Output Voltage: 0 V to 3.9 V
• Mounting Style: SMD/SMT
• Switching Frequency: 0 KHz to 400 KHz
• Operating Supply Voltage: 2.85 V to 3.9 V
• Supply Current: 2.5 mA to 10 mA
• Maximum Operating Temperature: + 95 C
• Fall Time: 300 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 300 ns
• Synchronous Pin: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1874T+000

Five digital input and five digital output pins are provid-
ed for monitoring and control.
By default (LOSC = 1, Table 02h, Register 89h), the
LOS pin is used to convert a standard comparator out-
put for loss of signal (LOS) to an open-collector output.
This means the mux shown in the Block Diagram by
default selects the LOS pin as the source for the
LOSOUT output transistor. The output of the mux can
be read in the STATUS byte (Lower Memory,
Register 6Eh) as the RXL bit. The RXL signal can be
inverted (INV LOS = 1) before driving the open-drain
output transistor using the XOR gate provided. Setting
LOSC = 0 configures the mux to be controlled by LOS
LO, which is driven by the output of the LOS quick trip
(Table 02h, Registers BEh and BFh). The mux setting
(stored in EEPROM) does not take effect until V
POA, allowing the EEPROM to recall.
The digital input IN1 and RSEL pins primarily serve to
meet the rate-select requirements of SFP and SFP+.
They also serve as general-purpose inputs. OUT1 and
Figure 12. Logic Diagram 1
BIAS MAX ENABLE
TXP LO ENABLE
TXP HI ENABLE
HBAL ENABLE
TXDC
TXP LO FLAG
TXP HI FLAG
TXD
HBAL FLAG
BIAS MAX
R
PU
V
CC
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________
TXDS
TXD
EXT
IN1, RSEL, OUT1, RSELOUT
OUT
FAULT RESET TIMER
OUT
IN
(130ms)
Digital I/O Pins
IN
LOS, LOSOUT
C
C
D
R
S
Q
Q
CC
>
RSELOUT are driven by a combination of the IN1,
RSEL, and logic dictated by control registers in the
EEPROM (Figure 13). The levels of IN1 and RSEL can
be read using the STATUS register (Lower Memory,
Register 6Eh). The open-drain output OUT1 can be
controlled and/or inverted using the CNFGB register
(Table 02h, Register 8Ah). The open-drain RSELOUT
output is software-controlled and/or inverted through
the Status register and CNFGA register (Table 02h,
Register 89h). External pullup resistors must be provid-
ed on OUT1 and RSELOUT to realize high logic levels.
TXDOUT is generated from a combination of TXF, TXD,
and the internal signal FETG. A software control identi-
cal to TXD is available (TXDC, Lower Memory, Register
6Eh). A TXD pulse is internally extended (TXD
time t
warnings related to the APC loop to allow for the loop to
stabilize. The nonlatching alarms and warnings are TXP
LO, LOS LO, and MON1–MON4 LO alarms and warn-
ings. In addition, TXP LO is disabled from creating
FETG. TXF is both an input and an output (Figure 12).
See the Transmit Fault (TXF) Output section for a
detailed explanation of TXF. Figure 12 shows that the
POWER-ON
RESET
SET BIAS REGISTER TO 0 AND
MAX3798/MAX3799
SET_IMOD TO 0
INITR1
FETG
BIAS MAX FLAG
TXP LO FLAG
TXP HI FLAG
HBAL FLAG
to inhibit the latching of low alarms and
MINT
TXDFLT
TXDFG
TXDIO
TXD
TXF, TXD, TXDOUT
TXF
EXT
TXDOUT
TXF
) by
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