DS1874T+ Maxim Integrated Products, DS1874T+ Datasheet - Page 29

• Manufacturer Part Number: DS1874T+
• Description: IC CTLR SFP+ ANLG LDD 28-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controllerr

Specifications of DS1874T+

• Number Of Channels: 1
• Voltage - Supply: 2.85 V ~ 3.9 V
• Current - Supply: 2.5mA
• Operating Temperature: -40°C ~ 95°C
• Package / Case: 28-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Number Of Outputs: 5
• Duty Cycle (max): 50 %
• Output Voltage: 0 V to 3.9 V
• Mounting Style: SMD/SMT
• Switching Frequency: 0 KHz to 400 KHz
• Operating Supply Voltage: 2.85 V to 3.9 V
• Supply Current: 2.5 mA to 10 mA
• Maximum Operating Temperature: + 95 C
• Fall Time: 300 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 300 ns
• Synchronous Pin: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1874T+000

Table 05h is empty by default. It can be configured to
contain the alarm- and warning-enable bytes from Table
01h, Registers F8h–FFh with the MASK bit enabled
(Table 02h, Register 89h). In this case Table 01h is
empty.
Table 06h contains a temperature-indexed LUT that
allows the APC set point to change as a function of
temperature to compensate for tracking error (TE). The
APC LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C and +100°C.
Table 07h contains a temperature-indexed LUT for con-
trol of DAC1. The LUT has 36 entries that determine the
DAC setting in 4°C windows between -40°C and +100°C.
Table 08h contains a temperature-indexed LUT for con-
trol of DAC2. The LUT has 36 entries that determine the
DAC setting in 4°C windows between -40°C and +100°C.
Auxiliary Memory (device A0h) contains 256 bytes of
EE memory accessible from address 00h–FFh. It is
selected with the device address of A0h.
See the Register Descriptions section for more com-
plete details of each byte’s function, as well as for
read/write permissions for each byte.
Figure 19. Memory Map
00h
I
2
C ADDRESS A0h
(256 BYTES)
EEPROM
FFh
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________
00h
80h
F8h
PASSWORD ENTRY
(PWE) (4 BYTES)
TABLE-SELECT
ENABLE ROW
(120 BYTES)
TABLE 01h
MEMORY
(8 BYTES)
LOWER
EEPROM
ALARM-
BYTE
7Fh
FFh
F7h
80h
E8h
TABLE CONTROL
CONFIGURATION
NONLOOKUP
TABLE 02h
3W CONFIG
REGISTERS
NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I
NOTE 2: TABLE 00h DOES NOT EXIST.
NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE
AND
IF ASEL = 1, THEN THE MAIN DEVICE I
TABLE 02h, REGISTER 8Ch.
MASK BIT IN TABLE 02h, REGISTER 89h.
FFh
E7h
80h
LOOKUP TABLE
TABLE 04h
(72 BYTES)
MOD
C7h
Many NV memory locations (listed within the Register
Descriptions section) are actually shadowed EEPROM
that are controlled by the SEEB bit in Table 02h,
Register 80h.
The DS1874 incorporates shadowed-EEPROM memory
locations for key memory addresses that can be written
many times. By default the shadowed-EEPROM bit,
SEEB, is not set and these locations act as ordinary
EEPROM. By setting SEEB, these locations function like
SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
Setting SEEB also eliminates the requirement for the
EEPROM write time, t
SEEB enabled do not affect the EEPROM, these
changes are not retained through power cycles. The
power-on value is the last value written with SEEB dis-
abled. This function can be used to limit the number of
EEPROM writes during calibration or to change the
monitor thresholds periodically during normal operation
helping to reduce the number of times EEPROM is writ-
ten. Figure 19 indicates which locations are shadowed
EEPROM.
ALARM-ENABLE ROW
F8h TABLE 05h
2
2
C SLAVE ADDRESS IS A2h.
C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN
(8 BYTES) FFh
80h TABLE 06h
TRACKING ERROR
LOOKUP TABLE
(36 BYTES) A3h
W
. Because changes made with
80h
Shadowed EEPROM
TABLE 07h
DAC1 LUT
A3h
80h
TABLE 08h
DAC2 LUT
A3h
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