C8051F350DK Silicon Laboratories Inc, C8051F350DK Datasheet - Page 204
C8051F350DK
Manufacturer Part Number
C8051F350DK
Description
DEV KIT FOR F350/351/352/353
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350, 351, 352, 353
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1083
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F350DK
Manufacturer:
SiliconL
Quantity:
8
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C8051F350/1/2/3
22.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 22.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
204
External Clock / 8
T2MH
0
0
1
SYSCLK / 12
T2XCLK
T2XCLK
0
1
X
0
1
Figure 22.5. Timer 2 8-Bit Mode Block Diagram
SYSCLK
External Clock / 8
TMR2H Clock
SYSCLK / 12
SYSCLK
Source
0
1
1
0
M
T
3
H
M
T
3
L
CKCON
M
T
2
H
M
T
2
L
M
T
1
M
T
0
TR2
S
C
A
1
S
C
A
0
Rev. 1.1
TCLK
TCLK
TMR2RLH
TMR2RLL
TMR2H
TMR2L
T2ML
Reload
Reload
0
0
1
T2XCLK
T2SPLIT
TF2LEN
T2XCLK
X
0
1
TF2H
TF2L
TR2
External Clock / 8
TMR2L Clock
SYSCLK / 12
SYSCLK
Source
Interrupt
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