C8051F350DK Silicon Laboratories Inc, C8051F350DK Datasheet - Page 45

• Manufacturer Part Number: C8051F350DK
• Description: DEV KIT FOR F350/351/352/353
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F350DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F35x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F350
• Silicon Family Name: C8051F35x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F350, 351, 352, 353
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1083

The offset calibration value adjusts the zero point of the ADC’s transfer function. It is stored as a two’s
complement, 24-bit number. An offset calibration which results in a full-scale positive (0x7FFFFF) or full-
scale negative (0x800000) result will cause an ADC error condition.
The Offset Calibration results are stored in registers ADC0COH, ADC0COM, and ADC0COL. The weight-
ing of the bits in the offset register (in LSBs) are shown below:
The gain calibration value adjusts the slope of the ADC’s transfer function. The gain calibration regsiter
can range from 0 to 2 – 2
ADC error condition.
The Gain Calibration results are stored in registers ADC0CGH, ADC0CGM, and ADC0CGL, as follows:
Example Decoding for Gain Register setting of 0x940000 (10010100 00000000 00000000b):
Slope Adjustment = 2
MSB 22
MSB 22
MSB 22
–
–2
2
2
0
15
23
2
2
2
14
–1
22
2
2
2
21
21
21
13
–2
21
ADC0COH
ADC0COH
ADC0CGH
2
2
2
20
20
20
12
–3
20
2
2
2
19
19
19
Figure 5.3. ADC0 Offset Calibration Register Coding
11
–4
19
Figure 5.4. ADC0 Gain Calibration Register Coding
0
2
2
2
18
18
18
+ 2
–5
18
10
–23
–3
2
2
17
17
17
2
17
–6
+ 2
9
. A gain calibration which results in either of these extremes will cause an
2
2
–5
16
16
16
2
16
–7
8
= 1.0 + 0.125 + 0.03125 = 1.15625
2
2
15
15
15
2
15
–8
7
24-bit ADC (C8051F350/1)
16-bit ADC (C8051F352/3)
2
2
14
14
14
2
14
–9
6
2
2
13
13
13
2
–10
13
5
ADC0COM
ADC0CGM
ADC0COM
2
Rev. 1.1
2
12
12
12
2
–11
12
4
2
2
11
11
11
2
–12
11
3
2
2
10
10
10
2
–13
10
2
2
2
2
9
–14
9
9
9
1
2
2
8
2
–15
8
8
8
0
C8051F350/1/2/3
2
2
2
7
–16
7
7
–1
7
2
2
2
6
–17
6
6
6
–2
2
2
2
5
–18
5
5
5
–3
ADC0COL
ADC0COL
ADC0CGL
2
2
2
4
–19
4
4
4
–4
2
2
2
3
–20
3
3
3
–5
2
2
2
2
–21
2
2
2
–6
2
2
2
1
–22
1
1
1
–7
LSB
LSB
2
LSB
2
2
–23
0
–8
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