C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 130

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F52x/F52xA/F53x/F53xA
SFR Definition 13.7. P0MAT: Port0 Match
SFR Definition 13.8. P0MASK: Port0 Mask
130
Bits7–0: P0MAT[7:0]: Port0 Match Value.
Bits7–0: P0MASK[7:0]: Port0 Mask Value.
R/W
R/W
Bit7
Bit7
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P0 & P0MASK) does not equal (P0MAT & P0MASK).
These bits select which Port pins will be compared to the value stored in P0MAT.
0: Corresponding P0.n pin is ignored and cannot cause a Port Match event.
1: Corresponding P0.n pin is compared to the corresponding bit in P0MAT.
R/W
R/W
Bit6
Bit6
R/W
R/W
Bit5
Bit5
R/W
R/W
Bit4
Bit4
Rev. 1.3
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
R/W
Bit0
R/W
Bit0
Reset Value
00000000
Reset Value
11111111
0xD7
0xC7