C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 99

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction, and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Table 10.1. Interrupt Summary
Reset
External Interrupt 0(INT0)
Timer 0 Overflow
External Interrupt 1(INT0)
Timer 1 Overflow
UART
Timer 2 Overflow
SPI0
ADC0 Window Compara-
tor
ADC0 End of Conversion
Programmable Counter
Array
Comparator Falling Edge
Comparator Rising Edge
LIN Interrupt
Voltage Regulator Dropout 0x006B
Port Match
Note: Software must set the RSTINT bit (LINCTRL.3) to clear the LININT flag.
Interrupt Source
Interrupt
0x0000
0x0003
0x000B
0x0013
0x001B
0x0023
0x002B
0x0033
0x003B
0x004B
0x0053
0x005B
0x0063
0x0073
0x0043
Vector
C8051F52x/F52xA/F53x/F53xA
Priority
Order
Top
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
RXOVRN (SPI0CN.4)
AD0INT (ADC0CN.5)
CP0RIF (CPT0CN.5)
CP0FIF (CPT0CN.4)
Rev. 1.3
TF2H (TMR2CN.7)
CCFn (PCA0CN.n)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
TF2L (TMR2CN.6)
LININT (LINST.3)
SPIF (SPI0CN.7)
CF (PCA0CN.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
Pending Flag
TF0 (TCON.5)
TF1 (TCON.7)
IE0 (TCON.1)
IE1 (TCON.3)
(ADC0CN.3)
AD0WINT
None
N/A
N/A
N/A N/A
N/A N/A
N/A N/A
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N*
N
N
N
N
N
N
N
N
Y
Y
Y
Y
EX0 (IE.0) PX0 (IP.0)
EX1 (IE.2) PX1 (IP.2)
ES0 (IE.4) PS0 (IP.4)
ET0 (IE.1)
ET1 (IE.3)
ET2 (IE.5)
EWADC0
Enabled
(EIE1.0)
(EIE1.1)
(EIE1.2)
(EIE1.3)
(EIE1.4)
(EIE1.5)
(EIE1.6)
(EIE1.7)
EADC0
EREG0
Enable
Always
EPCA0
ESPI0
ECPF
ECPR
EMAT
(IE.6)
ELIN
Flag
PT0 (IP.1)
PT1 (IP.3)
PT2 (IP.5)
PWADC0
(EIP1.0)
(EIP1.1)
(EIP1.2)
(EIP1.3)
(EIP1.4)
(EIP1.5)
(EIP1.6)
(EIP1.7)
Priority
Control
Highest
PREG0
PADC0
PPCA0
Always
PSPI0
PCPR
PMAT
PCPF
(IP.6)
PLIN
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