C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 40
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F52x/F52xA/F53x/F53xA
Table 3.4. Pin Definitions for the C8051F53x and C805153xA (TSSOP 20)
40
*Note: Please refer to Section “20. Device Specific Behavior” on page 209.
RST/C2CK
P0.0/V
V
Name
C2CK
RST/
P0.0/
V
GND
P0.2
P0.1
P1.7
REGIN
V
V
REF
DD
GND
P1.7
P1.6
P1.5
P0.2
P0.1
REGIN
V
REF
DD
‘F53xA ‘F53x
Pin Numbers
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
D I/O or
D I/O or
D I/O or
D I/O or
A O or
D I/O
D I/O
Type
D In
A In
A In
A In
A In
P1.1
P0.3
P0.4/TX
P0.5/RX
P0.6/C2D
P1.3
P0.7/XTAL1
P1.0/XTAL2
P1.2/CNVSTR
P1.4
Description
Port 0.2. See Port I/O Section for a complete description.
Port 0.1. See Port I/O Section for a complete description.
Device Reset. Open-drain output of internal POR or V
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.7 on page 32. A 1 k pullup to V
is recommended. See Reset Sources Section for a complete
description.
Clock signal for the C2 Debug Interface.
Port 0.0. See Port I/O Section for a complete description.
External V
Ground.
Core Supply Voltage.
On-Chip Voltage Regulator Input.
Port 1.7. See Port I/O Section for a complete description.
Rev. 1.3
REF
Input. See V
RST/C2CK
P0.0/V
V
GND
P1.7
P1.6
P1.5
P0.2
P0.1
REGIN
V
REF
DD
REF
Section.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P1.1
P0.6/C2D
P0.3/TX
P0.4/RX
P0.5
P0.7/XTAL1
P1.0/XTAL2
P1.2/CNVSTR
P1.3
P1.4
DD
monitor.
REGIN
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