C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 134

BOARD PROTOTYPE W/C8051F530

C8051F530-TB

Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F530-TB

Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F52x/F52xA/F53x/F53xA
14. Oscillators
C8051F52x/F52xA/F53x/F53xA devices include a programmable internal oscillator, an external oscillator
drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and
OSCICL registers, as shown in Figure 14.1. The system clock (SYSCLK) can be derived from the internal
oscillator, external oscillator circuit. Oscillator electrical specifications are given in Table 2.10 on page 34.
14.1. Programmable Internal Oscillator
All C8051F52x/53x devices include a programmable internal oscillator that defaults as the system clock
after a system reset. The internal oscillator period can be programmed via the OSCICL and OSCIFIN reg-
isters, shown in SFR Definition 14.2 and SFR Definition 14.3. On C8051F52x/53x devices, OSCICL and
OSCIFIN are factory calibrated to obtain a 24.5 MHz frequency.
Electrical specifications for the precision internal oscillator are given in Table 2.10 on page 34. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64,
or 128 as defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
134
VDD
Option 2
XTAL2
Option 1
Option 4
10M
XTAL2
Option 3
XTAL2
XTAL1
XTAL2
Figure 14.1. Oscillator Diagram
OSCICL
Circuit
Input
Programmable
Internal Clock
Generator
OSCXCN
OSC
EN
Rev. 1.3
OSCIFIN
IOSC
EXOSC
OSCICN
n
CLKSEL
SYSCLK

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