C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 179

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SFR Definition 17.15. LIN0SIZE: LIN0 Message Size Register
SFR Definition 17.16. LIN0DIV: LIN0 Divider Register
Bit7:
Bit6–4:
Bit3–0:
Bit7–0:
ENHCHK
R/W
Bit7
Bit7
R
DIVLSB[7:0]: LIN Baud Rate Divider Least Significant Bits.
The 8 least significant bits for the baud rate divider. The 9th and most significant bit is the
DIV9 bit (LIN0MUL.0). The valid range for the divider is 200 to 511.
ENHCHK: Checksum Selection Bit.
0: Use the classic, specification 1.3 compliant checksum. Checksum covers the data bytes.
1: Use the enhanced, specification 2.1 compliant checksum. Checksum covers data bytes
and protected identifier.
UNUSED. Read = 000b. Write = don’t care.
LINSIZE3–0: Data Field Size.
0000: 0 data bytes
0001: 1 data byte
0010: 2 data bytes
0011: 3 data bytes
0100: 4 data bytes
0101: 5 data bytes
0110: 6 data bytes
0111: 7 data bytes
1000: 8 data bytes
1001-1110: RESERVED
1111: Use the ID[1:0] bits (LIN0ID[5:4]) to determine the data length.
R/W
Bit6
Bit6
R
-
R/W
Bit5
Bit5
R
-
R/W
Bit4
Bit4
C8051F52x/F52xA/F53x/F53xA
R
-
Rev. 1.3
R/W
Bit3
Bit3
R
R/W
Bit2
Bit2
R
LINSIZE[3:0]
R/W
Bit1
Bit1
R
R/W
Bit0
Bit0
Address: 0x0B (indirect)
Address: 0x0C (indirect)
R
Reset Value
Reset Value
00000000
00000000
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