C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 46

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F52x/F52xA/F53x/F53xA
Table 3.7. Pin Definitions for the C8051F53x and C805153xA (QFN 20)
46
Note: Please refer to Section “20. Device Specific Behavior” on page 209.
CNVSTR
V
Name
C2CK
RST/
P0.0/
V
P1.2/
GND
P1.7
P1.6
P1.5
P1.4
P1.3
P1.1
REGIN
V
REF
DD
‘F53xA ‘F53x
Pin Numbers
10
11
12
1
2
3
4
5
6
7
8
9
10
12
11
1
2
3
4
5
6
7
8
9
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
A O or
D I/O
D I/O
Type
D In
D In
A In
A In
A In
A In
A In
A In
A In
A In
Description
Device Reset. Open-drain output of internal POR or V
An external source can initiate a system reset by driving this pin
low for at least the minimum RST low time to generate a system
reset, as defined in Table 2.7 on page 32. A 1 k pullup to V
is recommended. See Reset Sources Section for a complete
description.
Clock signal for the C2 Debug Interface.
Port 0.0. See Port I/O Section for a complete description.
External V
Ground.
Core Supply Voltage.
On-Chip Voltage Regulator Input.
Port 1.7. See Port I/O Section for a complete description.
Port 1.6. See Port I/O Section for a complete description.
Port 1.5. See Port I/O Section for a complete description.
Port 1.4. See Port I/O Section for a complete description.
Port 1.3. See Port I/O Section for a complete description.
Port 1.2. See Port I/O Section for a complete description.
External Converter start input for the ADC0, see Section “4. 12-Bit
ADC (ADC0)” on page 52 for a complete description.
Port 1.1. See Port I/O Section for a complete description.
Rev. 1.3
REF
Input. See V
REF
Section.
DD
monitor.
REGIN