C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 8

• Manufacturer Part Number: C8051F530-TB
• Description: BOARD PROTOTYPE W/C8051F530
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F530-TB

• Contents: Board
• Processor To Be Evaluated: C8051F52xA and C8051F53xA
• Interface Type: USB
• Lead Free Status / RoHS Status: Vendor undefined / Vendor undefined
• For Use With/related Products: C8051F530
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F52x/F52xA/F53x/F53xA
8
Figure 14.2. 32 kHz External Crystal Example ...................................................... 139
Figure 15.1. UART0 Block Diagram ...................................................................... 143
Figure 15.2. UART0 Baud Rate Logic ................................................................... 144
Figure 15.3. UART Interconnect Diagram ............................................................. 145
Figure 15.4. 8-Bit UART Timing Diagram .............................................................. 145
Figure 15.5. 9-Bit UART Timing Diagram .............................................................. 146
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram ......................... 147
Figure 16.1. SPI Block Diagram ............................................................................ 150
Figure 16.2. Multiple-Master Mode Connection Diagram ...................................... 153
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............ 153
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............ 153
Figure 16.5. Data/Clock Timing Relationship ........................................................ 155
Figure 16.6. SPI Master Timing (CKPHA = 0) ....................................................... 160
Figure 16.7. SPI Master Timing (CKPHA = 1) ....................................................... 160
Figure 16.8. SPI Slave Timing (CKPHA = 0) ......................................................... 161
Figure 16.9. SPI Slave Timing (CKPHA = 1) ......................................................... 161
Figure 17.1. LIN Block Diagram ............................................................................ 163
Figure 18.1. T0 Mode 0 Block Diagram ................................................................. 182
Figure 18.2. T0 Mode 2 Block Diagram ................................................................. 183
Figure 18.3. T0 Mode 3 Block Diagram ................................................................. 184
Figure 18.4. Timer 2 16-Bit Mode Block Diagram ................................................. 189
Figure 18.5. Timer 2 8-Bit Mode Block Diagram ................................................... 190
Figure 18.6. Timer 2 Capture Mode Block Diagram .............................................. 191
Figure 19.1. PCA Block Diagram ........................................................................... 194
Figure 19.2. PCA Counter/Timer Block Diagram ................................................... 195
Figure 19.3. PCA Interrupt Block Diagram ............................................................ 196
Figure 19.4. PCA Capture Mode Diagram ............................................................. 197
Figure 19.5. PCA Software Timer Mode Diagram ................................................. 198
Figure 19.6. PCA High-Speed Output Mode Diagram ........................................... 199
Figure 19.7. PCA Frequency Output Mode ........................................................... 200
Figure 19.8. PCA 8-Bit PWM Mode Diagram ........................................................ 201
Figure 19.9. PCA 16-Bit PWM Mode ..................................................................... 202
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled ................................ 203
Figure 20.1. Device Package—TSSOP 20 ............................................................ 209
Figure 20.2. Device Package—QFN 20 ................................................................ 209
Figure 20.3. Device Package—DFN 10 ................................................................ 210
Figure 21.1. Typical C2 Pin Sharing ...................................................................... 214
Rev. 1.3