C8051F530-TB Silicon Laboratories Inc, C8051F530-TB Datasheet - Page 73
C8051F530-TB
Manufacturer Part Number
C8051F530-TB
Description
BOARD PROTOTYPE W/C8051F530
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F530-TB.pdf
(218 pages)
Specifications of C8051F530-TB
Contents
Board
Processor To Be Evaluated
C8051F52xA and C8051F53xA
Interface Type
USB
Lead Free Status / RoHS Status
Vendor undefined / Vendor undefined
For Use With/related Products
C8051F530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Important Note About the V
the internal V
should be configured as an analog pin, and skipped by the Digital Crossbar. To configure P0.0 as an ana-
log pin, clear Bit 0 in register P0MDIN to 0. To configure the Crossbar to skip P0.0, set Bit 0 in register
P0SKIP to 1. Refer to Section “13. Port Input/Output” on page 119 for complete Port I/O configuration
details.
The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temper-
ature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor
result in meaningless data.
SFR Definition 5.1. REF0CN: Reference Control
Bits7–6: RESERVED. Read = 00b. Must write 00b.
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Reserved Reserved
R/W
Bit7
ZTCEN: Zero-TempCo Bias Enable Bit.
This bit must be set to 1b before entering oscillator suspend mode.
0: ZeroTC Bias Generator automatically enabled when needed.
1: ZeroTC Bias Generator forced on.
REFLV: Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference.
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.2 V.
REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: V
1: V
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Analog Bias Generator automatically enabled when needed.
1: Internal Analog Bias Generator on.
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the V
REF
REF
DD
. When using either an external voltage reference or the internal reference circuitry, P0.0
R/W
Bit6
used as voltage reference.
pin used as voltage reference.
ZTCEN
R/W
Bit5
REF
Pin: Port pin P0.0 is used as the external V
REFLV
R/W
Bit4
C8051F52x/F52xA/F53x/F53xA
Rev. 1.3
REFSL
R/W
Bit3
TEMPE
R/W
Bit2
BIASE
R/W
Bit1
REF
input and as an output for
REFBE
R/W
Bit0
REF
SFR Address:
00000000
Reset Value
pin.
0xD1
73
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