MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet
MPC8272ADS
Specifications of MPC8272ADS
Related parts for MPC8272ADS
MPC8272ADS Summary of contents
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... MPC8272ADSUG MPC8272ADS User Guide 3/2004 Rev. 0.1 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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... Paragraph Section Number Number 1.1 MPC8272ADS Specifications ............................................................................. 1-1 1.2 MPC8272ADS Features ...................................................................................... 1-2 Hardware Preparation and Installation 2.1 Unpacking Instructions ........................................................................................ 2-1 2.2 Hardware Preparation .......................................................................................... 2-1 2.2.1 Setting the 2.2.2 Setting MODCK(1:3) for PLLs Multiplication Factor—SW5 (#6–#8) .......... 2-3 2.2.3 Setting Hard Reset Configuration Source—JP9.............................................. 2-4 2 ...
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... Installation Instructions........................................................................................ 3-1 3.1.1 Host-Controlled Operation .............................................................................. 3-1 3.1.2 Stand Alone Operation..................................................................................... 3-2 3.1.3 COP/JTAG Connector—P21 ........................................................................... 3-3 3.1.4 Terminal to MPC8272ADS RS-232 Connection............................................. 3-3 3.1.5 10/100-Base-T Ethernet Ports Connection ...................................................... 3-4 3.1.6 Memory Installation......................................................................................... 3-4 3.1.6.1 Flash Memory SIMM Installation ............................................................... 3-4 4.1 Controls and Indicators ........................................................................................ 4-1 4.1.1 Power-On RESET Switch— ...
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Paragraph Number 4.1.30 Fast Ethernet Port 2 Full Duplex Indicator—LD6........................................... 4-6 4.1.31 General Purpose Led 1 Indicator—LD25........................................................ 4-6 4.1.32 Fast Ethernet Port 2 100Base-Tx Indicator—LD7 .......................................... 4-6 4.1.33 USB Enabled Indicator—LD21....................................................................... 4-6 4.1.34 Ethernet Port 2 LINK Indicator—LD9............................................................ 4-7 4.1.35 ...
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... Standby Rail ............................................................................................. 7-3 7.1.4 V Rail ........................................................................................................ 7-3 DDH 7.1.4.1 V Bus..................................................................................................... 7-3 DDL 7.1.4.2 12-V Rail ..................................................................................................... 7-4 7.1.4.3 -12-V Rail .................................................................................................... 7-4 7.2 Connectors ........................................................................................................... 7-4 7.2.1 ATX Power Connector..................................................................................... 7-4 7.2.2 Fast Ethernet Port Connectors ......................................................................... 7-4 Contents Chapter 6 Memory Map Chapter 7 Physical Properties MPC8272ADS User Guide ...
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Paragraph Number 7.2.3 ATM 155 Port Connection............................................................................... 7-5 7.2.4 RS232 Port Connector ..................................................................................... 7-5 7.2.5 CPM Expansion Connector ............................................................................. 7-5 7.2.6 COP/JTAG Port Connector.............................................................................. 7-5 7.2.7 Logic Analyzer Connectors ............................................................................. 7-5 7.2.8 Mach’s In System Programming (ISP) Connector .......................................... 7-5 ...
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... Paragraph Number Contents Title MPC8272ADS User Guide Page Number ...
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... Figure Number 1-1 MPC8272ADS Block Diagram................................................................................... 1-4 2-1 MPC8272ADS Top Side Part Location Diagram ....................................................... 2-2 2-2 V Trimmer—RP1 ................................................................................................. 2-3 DDL 2-3 SW5 Description ......................................................................................................... 2-4 2-4 Hard Reset Configuration Source Selection—JP9...................................................... 2-5 2-5 SW2 Description ......................................................................................................... 2-6 2-6 Clock Source Selection ............................................................................................... 2-7 2-7 FCC1 Ethernet Mode Selection ...
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... Figures MPC8272ADS User Guide ...
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... BCSR4 Description................................................................................................... 5-32 5-19 BCSR5 to BCSR7 Description ................................................................................. 5-33 5-20 COP/JTAG Port Signals Description ........................................................................ 5-34 6-1 MPC8272ADS Memory Map—Flash (or BCSR) as Boot Device............................. 6-1 6-2 MPC8272ADS Memory Map—E2PROM as Boot Device........................................ 6-3 6-3 BCSR/Flash Power On Reset Configuration .............................................................. 6-6 6-4 E2PROM Power On Reset Configuration .................................................................. 6-6 6-5 SIU Register Programming ...
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... P1—CPM Expansion Connector ................................................................................ 8-4 8-5 P26, P28, P29—PCI Connectors............................................................................... 8-13 8-6 P31—ATX Power Supply Connector ....................................................................... 8-15 8-7 P3—Lattice ISP Connector ....................................................................................... 8-16 8-8 P2—System Expansion Connector ........................................................................... 8-17 8-9 P16, P19—USB Connectors ..................................................................................... 8-22 Tables Title MPC8272ADS User Guide Page Number ...
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... The primary objective of this manual is to describe the functionality of the MPC8272ADS board. It contains operational, functional and general information about the MPC8272ADS. This board is meant to serve as a platform for software and hardware development for the MPC8272 processor in a TEPBGA package (516 Pins in Hip7). The high-performance MPC8272 PowerQUICC II™ ...
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... Chapter 4, “Operating Instructions,” provides information about controls and indicators for the MPC8272ADS. • Chapter 5, “Module Design,” provides information about MPC8272ADS reset and reset configuration, the clock generator, bus configuration, buffering, the chip-select generator, synchronous DRAM, Flash memory, and E • ...
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MPC8272 Documentation Supporting documentation for the MPC8272 can be accessed through the world-wide web at www.motorola.com/semiconductors. specifications, reference materials, and detailed applications notes. Architecture Documentation Architecture documentation is organized in the following types of documents: • Manuals—These books provide details ...
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... Instruction mnemonics are shown in lowercase bold. italics Italics indicate variable command parameters, for example, bcctrx. Book titles in text are set in italics. Internal signals are set in italics, for example, qual BG. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number MPC8272ADS User Guide ...
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... Acronyms and Abbreviations Table i contains acronyms and abbreviations that appear in this document. Table i. Acronyms and Abbreviated Terms MPC8272ADS ADS board For MPC8272 processor PQ2 PowerQUICC II MPC8275 PowerQUICC II Hip7 in TEPBGA package VOYAGER ...
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... Table i. Acronyms and Abbreviated Terms (continued) MPC8272ADS ADS board For MPC8272 processor DIMM Dual in-line memory module SIMM Single in-line memory module TBD To be defined UPM User programmable machine EVB Evaluation board GPCM General purpose chip-select machine GPL General purpose line ...
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... Chapter 1 Overview The primary objective of this manual is to describe the functionality of the MPC8272ADS board. It contains operational, functional and general information about the MPC8272ADS. This board is meant to serve as a platform for software and hardware development for the MPC8272 processor in a TEPBGA package (516 Pins in Hip7). The high-performance MPC8272 PowerQUICC II™ ...
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... Length Width Thickness 1.2 MPC8272ADS Features This section summarizes the features of the MPC8272ADS. Major features are the following: • Supports MPC8272 (Hip7) processor • 64-bit PowerQUICC II Communication Processor, running 100MHz external bus frequency • 64-MByte synchronous DRAM (soldered on-board), residing on 60X bus (PBI mode), controlled by SDRAM machine. Hard reset is applied by depressing BOTH Soft Reset & ...
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... Separate power-on reset push button, soft / hard reset push button, and ABORT push button • ATX power supply • 1.3V to 1.7V (Hip7) internal logic operation voltage • Software option switch provides 8 S/W options using BCSR. Figure 1-1 shows the MPC8272ADS block diagram. Chapter 1. Overview MPC8272ADS Features ...
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... DATA Transceivers & SCC1 Reset, Main Interrupts Clock SCC4 FCC2 FCC1 Logic Analyzer Mictors CPM Figure 1-1. MPC8272ADS Block Diagram 60x Bus 60X Bus Add. 60X Bus Data. 60X Bus (buffered) 3.3V<->5V Address Latches MPC8272ADS User Guide Logic Analyzer Mictors 3.3V SDRAM ...
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... Hardware Preparation To ensure that the desired configuration is selected to produce proper operation of the MPC8272ADS board, changes of the dip-switch settings may be required before installation. The location of the switches, indicators, dip-switches, and connectors is illustrated in Figure 2-1. Boards are factory-tested and shipped with dip-switch settings as described in the following tested graphs ...
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... PC parallel port (P27). Selected automatically by connecting parallel cable. • Force PC parallel port (P27) connection using jumper JP12 • ATX power supply on/off switch using SW4 JP5 JP1 Figure 2-1. MPC8272ADS Top Side Part Location Diagram MPC8272ADS User Guide JP8 JP10 SW4 P21 ...
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Setting the VDDL The level tuned using RP1 and is in the range DDL measured upon JP13, using a DVM or any other high-input impedance voltage measuring device. V ...
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... MODCKH0 1 MODCKH1 2 MODCKH2 3 MODCKH3 4 5 MODCK1 6 MODCK2 7 MODCK3 8 SW5 Factory Set Figure 2-3. SW5 Description Switch OFF ON OFF OFF ON OFF ON OFF OFF OFF OFF MPC8272ADS User Guide MODCKH0 MODCKH1 MODCKH2 MODCKH3 MODCK1 MODCK2 MODCK3 Switch 8 ON OFF ON OFF ON OFF ON OFF ...
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When a jumper is placed between positions 1–2 of JP9, the hard reset configuration source is a memory (FLASH/EEPROM) as configured by switch SW6-1. When a jumper is set between positions 2–3 of JP7, the hard reset configuration source is ...
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... When set high, the DLL is enabled. When switch SW6 # the OFF position, its corresponding PCI_DLL line is pulled-high (‘1’ - enabled). When at the ON position, pulled-down (‘0’ - disabled) (see Figure 2-5 PCI_DLL (ON) 2 PCI_ARBITER (OFF) 1 EEPROM BOOT SW2 Factory Set Figure 2-5. SW2 Description MPC8272ADS User Guide ...
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Clock-In Source Selection The main clock source can be selected between an external (off-board) source by connecting on-board clock oscillator. The selection is done by setting JP1. When a jumper is placed between positions 1–2 ...
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... The USB port supports two modes, host and slave. The selection is done by setting JP8. When a jumper is placed between positions 1–2 of JP8, the slave mode is enabled. When a jumper is placed between positions 2–3 of JP8, the host mode is enabled (see Figure 2-9). 3 NOTE MPC8272ADS User Guide JP10 ...
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JP8 1 2 Slave Mode Figure 2-9. USB Mode Selection 2.2.13 COP/JTAG Connection Either of two options can establish connection to the COP port of the PowerQUICC II: COP/JTAG connector or a parallel port of a PC. The COP/JTAG connector ...
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... Hardware Preparation MPC8272ADS User Guide ...
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... Chapter 3 Installation Instructions This chapter provides installation instructions for the MPC8272ADS. 3.1 Installation Instructions When the MPC8272ADS has been configured as desired by the user, it can be installed according to the required working environment as follows: • Host-controlled operation • Stand-alone 3.1.1 Host-Controlled Operation In this configuration, the MPC8272ADS is controlled by a host computer using the COP port, which is a subset of the JTAG port ...
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... Ethernet port, ATM155 port, and so on. Operating in this mode requires programming an application program into the board’s Flash memory. Host Computer ATM 155 (optics) Figure 3-3. Stand Alone Configuration ATX Power Supply P5 P16 RS232 Ethernet P1A/P1B MPC8272ADS User Guide ATX Power Supply P5 ...
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... COP/JTAG Connector—P21 The MPC8272ADS COP interface connector P21 is a 16-pin, male header connector. The connection between the MPC8272ADS and the COP controller 16-line flat cable supplied with the COP controller board obtained from a third party developer. Figure 3-4 shows the pin configuration of the connector. ...
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... A standard cable that has two RJ45/8 jacks on its ends connects the 10/100-Base-T ports to the network. The pinout of P10 and P23 is described in Table 8-2. 3.1.6 Memory Installation The MPC8272ADS is supplied with one type of memory module, the Flash memory SIMM. 3.1.6.1 Flash Memory SIMM Installation ...
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... The ABORT switch ends program execution by issuing a level 0 interrupt to the MPC8272. If the ADS is in standalone mode, the user must provide a means for handling the interrupt, because the MPC8272ADS does not have a resident debugger. The ABORT switch signal is debounced and may be disabled by software. ...
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... The job of removing JP13 and soldering the current meter connections instead is very delicate and should be done by a skilled technician. If this process is done by unskilled hands or repeated more than 3 times, the MPC8272ADS can be permanently damaged. 4.1.8 Thermal Sense Connector—JP7 Two dedicated pins THERM(0:1) provide a way to take internal temperature measurements of the MPC8272 ...
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... The job of removing JP14 and soldering current meter connections instead is very delicate, and should be done by a skilled technician. If this process is done by unskilled hands or repeated more than 3 times, the MPC8272ADS can be permanently damaged. 4.1.10 V Source Selector—JP4 PP JP4 selects the source for V ...
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... Controls and Indicators 4.1.11 GND Bridges The MPC8272ADS has seven GND bridges that are meant to assist general measurements and the logic-analyzer connection. When connecting to a GND bridge, use only insulated GND clips. Un-insulated clips may cause short-circuits that touch hot points around them. Failure to use insulated GND clips can permanently damage the MPC8272ADS. 4.1.12 Power O.K. Indicator— ...
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RUN Indicator—LD18 When the green RUN led - LD18 is lit, it indicates that the MPC8272 is performing cycles on the PPC bus. When dark, the MPC8272 is either running internally or stuck. 4.1.20 ATM ON Indicator—LD19 When the ...
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... Fast Ethernet Port 2 100Base-Tx Indicator—LD7 When the DM9161 on FCC2 is enabled and is in 100 Mbps operation mode, the green led LD7 lights. 4.1.33 USB Enabled Indicator—LD21 The yellow USB enable LED indicates that the USB transceiver is connected to the MPC8272. MPC8272ADS User Guide ...
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Ethernet Port 2 LINK Indicator—LD9 The yellow Ethernet twisted pair link integrity LED indicator (LINK) lights to indicate good link integrity on the 10/100-Base-T port. When the link integrity fails, LD9 is off. 4.1.35 Ethernet Port 2 Tx/Rx Indicator—LD8 ...
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... Controls and Indicators MPC8272ADS User Guide ...
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... This chapter provides information about the functionality and design details of the various modules that constitute the MPC8272ADS. 5.1 Reset and Reset Configuration The following are reset sources on the MPC8272ADS: • Power-on reset • Manual hard reset • Manual soft reset • PCI bus reset • ...
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... PCI bus frequency by two. When reset low, the PCI bus frequency is as determined by the MODCK(1:3) and PCI_MODCKH(0:3) signals. 5.1.3 Hard Reset Hard reset may be generated on the MPC8272ADS by the following sources: • COP/JTAG port • Manual hard reset • MPC8272’s internal sources ...
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... Because the HRESET line may be driven internally by the MPC8272, it must be driven to the MPC8272 with an open-drain gate. If off-board hardware connected to the MPC8272ADS is to drive HRESET line, it should do so with an open-drain gate, to avoid contention over this line. When hard reset is generated, the MPC8272 is reset in a destructive manner, that is, the hard reset configuration is re-sampled and all registers (except for the PLL’ ...
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... E PROM or as default in the BCSR, while the other seven words are not initialized, as there are no additional MPC8272 on the MPC8272ADS. The default configuration word is shown in Table 5-1 for the FLASH and in Table 5-2 for the E configuration is 256 Bytes long and should start at address 0x100. ...
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Table 5-1. BCSR/FLASH Hard Reset Configuration Word (continued) Data Prog Field Bus Value Bits [Bin] L2CPC 8:9 ‘01’ DPPC 10:11 ‘11’ Reserved 12 ’0’ ISB 13:15 ’010’ BMS 16 ’0’ BBD 17 ’0’ MMR 18:19 ’11’ LBPC 20:21 ’01’ APPC ...
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... DBB/IRQ3 pin is DBB Mask Masters Requests. Boot Master is 60x. Local Bus pins function as PCI bus. MODCK1/AP(1)/TC(0) functions as BKSEL0 MODCK2/AP(2)/TC(1) functions as BKSEL1 MODCK3/AP(3)/TC(2) functions as BKSEL2 IRQ7~/APE~ functions as IRQ7~ CS11~/AP(0) functions as CS11~ MPC8272ADS User Guide Offset In Value Flash [Hex] [Hex ...
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Table 5-2. E PROM Hard Reset Configuration Word (continued) Data Prog Field Bus Value Bits [Bin] CS10PC 24:25 ’01’ ALD_EN 26 ’0’ PCI_MODCK 27 ’1’ 1 MODCK_HI 28:31 ‘1010’ 1 Applies only ONCE after power-up reset. The PCI configuration ...
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... Since the SRESET line may be driven internally by the MPC8272, it must be driven by an open-drain gate, to avoid contention over that line. If off-board H/W connected to the MPC8272ADS is to drive SRESET line, then, it should do so with an open-drain gate, this, to avoid contention over this line. 5.1.4.3 ...
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Local Interrupter The following external interrupts are applied to the MPC8272 using its interrupt controller: • ABORT (NMI) • ATM UNI interrupt • Fast Ethernet PHY interrupt • PCI interrupt 5.1.6.1 ABORT Interrupt The ABORT (NMI) is generated by ...
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... PCI0_INTD PCI Slot 0 INTD. PCI Slot 0 Interrupt D: ‘0’ interrupt was requested ‘1’ interrupt was requested and waiting to be handled SLOT 0 A INTA B INTB PCI Interrupt C INTC Controller D INTD Function MPC8272ADS User Guide SLOT SLOT PON T DEF ...
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Table 5-3. PCI Interrupt Register Description (continued) BI MNEMONIC T 4 PCI1_INTA PCI Slot 1 INTA. PCI Slot 1 Interrupt A: ‘0’ interrupt was requested ‘1’ interrupt was requested and waiting to be handled 5 PCI1_INTB ...
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... Mask PCI Slot 2 INTC. Mask PCI Slot 2 Interrupt C: ‘0’ - interrupt is available ‘1’ - interrupt is masked Mask PCI Slot 2 INTD. Mask PCI Slot 2 Interrupt D: 11 MPCI2_INTD ‘0’ - interrupt is available ‘1’ - interrupt is masked 12-31 Reserved Un-implemented Function MPC8272ADS User Guide PO N ATT R/W 0 R/W 0 R/W ...
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Clock Generator The two main clock circuits on board are the following: • MPC8272 system clock • PCI clock 5.2.1 MPC8272 Clock The MPC8272 requires a single clock source as the main clock source. All MPC8272 60x bus timings ...
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... To allow a configuration word stored in the Flash/E Low Skew Clock Buffer MPC8272 OUT1 DLLOUT IN OUT2 CLKIN1 CLKIN2 OUT4 OUT3 3 . Data conflicts are avoided in case an unbuffered 2 PROM memory to become active. MPC8272ADS User Guide PCI Device #1 PCI Device #2 PCI Device #3 2 PROM, 2 buffered board address ...
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... When a CS region assigned to a buffered data transceivers are disabled during access to that region, avoiding possible over data lines. The MPC8272 chip-select assignments to the various memories / registers on the MPC8272ADS are shown in Table 5-5. Table 5-5. MPC8272ADS Chip Select Assignments Chip Select: CS0 ...
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... SDRAM machine of the MPC8272. Before that can occur, the SDRAM machine of the MPC8272 must be initialized. CS2 CS0 SDRAS RAS SDCAS CAS SDWE WE BANKSEL(1:2) BA(1:0) A17 A11 SDA10 A10 A19 A9 A(20:28) A(8:0) SDDQM(0:7) DQMB(0:7) D(0:63) DQ(0:63) CKE SYSCLK CLK MT48LC8M16A2-6 MPC8272ADS User Guide ...
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... Flash SIMM inserted to the MPC8272ADS. The access time of the Flash memory provided with the MPC8272ADS is 95 nsec. However, devices with different delay are supported as well. By reading the delay section Value ’ ...
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... ADDRESS(7:29) WE0 WE1 WE2 WE3 POE CS1 FLASH CS2 CS CS3 CS4 PD1 PD2 PD3 PD4 PD5 PD6 PD7 MPC8272ADS User Guide 1 , the debugger or any FLASH SIMM D(31:0) A(22:0) WE0 WE1 WE2 WE3 POE CS1 CS2 CS3 CS4 PD1 PD2 PD3 PD4 ...
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... Flash, Motorola recommends leaving the jumper open so that no V applied to the Flash SIMM. 2 5.8 E PROM Memory The MPC8272ADS is provided with 8KBytes The E PROM resides on a socket in case it is desired to replace or re-program a different configuration for the board. The E Reset Configuration Word during power-on reset and for storing the PCI configuration data ...
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... PCI configuration space. The MPC8272 also includes an on-chip arbiter which enables arbitration three PCI masters. Only three PCI slots are supported on the MPC8272ADS because of the Arbiter capacity. Each slot can host either a PCI master or PCI target. The MPC8272 as a Bridge can support more PCI devices but that will require extra slots that can host PCI targets only. ...
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... The 3.3V restriction is due to the MPC8272 which is not 5V compliant. The PCI bus layout is shown in Figure 5-8 Special care was taken when the layout of the MPC8272ADS was done so that the PCI standard recommendations are followed strictly. ...
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... Communication Ports 5.10 Communication Ports The MPC8272ADS has several communication ports, to allow convenient evaluation of the CPM features. Obviously not possible to provide all types of communication interfaces supported by the CPM, but it is made convenient to connect any communication interface devices to the MPC8272 via the CPM Expansion connectors, residing on the edge of the board ...
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... The DM9161 are connected to FCC1 and FCC2 of the MPC8272 via MII or RMII interface, which is used for both - devices’ control and data path. The initial configuration of the DM9161 on the MPC8272ADS is set by external resistors - 100Base-Tx Full Duplex in MII mode. The selection between MII/RMII for FCC1 and FCC2 is done by jumpers JP5 and JP10 respectively ...
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... In the list below, the directions ’I’,’O’, and ’I/O’ are relative to the MPC8272ADS board. (i.e.’I’ means input to the MPC8272ADS) • CD (O) - Data Carrier Detect. This line is always asserted by the MPC8272ADS. • TX (O) - Transmit Data. • RX (I) - Receive Data. ...
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... CTS (O) - Clear To Send. This line is always asserted by the MPC8272ADS. • 5.10.4 USB Port The USB port resides on the MPC8272ADS and is driven by the USB port of the MPC8272 through SCC3. A dedicated USB transceiver - the PDIUSBP11 by PHILIPS is provided, along with a tri-state buffer, separating this port from the MPC8272’s USB port, this to allow Port disable option and off-board use of MPC8272 USB pins ...
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... PCI cards Present Detect and card type • Local bus mode Since part of the MPC8272ADSs’ modules are controlled by the BCSR and since they may be disabled in favor of external hardware, the enable signals for these modules are presented at the CPM expansion connectors, so that off- board hardware may be mutually exclusive enabled with on-board modules ...
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... General Purpose Led 2. General purpose Led to be used by the user Reserved Un-implemented 5.11.2 BCSR1 Board Control—Status Register 1 The BCSR1 is a control register on the MPC8272ADS accessed at offset 4 from BCSR base address. It may be read or written at any time Power-On reset. The fields are described in Table 5-8 BIT MNEMONIC ...
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... System expansion connector. The revision option for the external tools are shown in Table 5-15 1 Provided that BCSR is not disabled. Function 1 . BCSR2s’ various fields are described Table 5-9. BCSR2 Description Function MPC8272ADS User Guide PON ATT. DEF 1 R,W 1 R,W 1 ...
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... Un-implemented BVERN(0:1) Board Version Number (0:1). This field represents the version code, hard-assigned to the MPC8272ADS. See Table 5-13, for version encoding BREVN(0:1) Board Revision Number (0:1). This field represents the revision code, hard-assigned to the MPC8272ADS. See Table 5-14, for revisions’ ...
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... Revision Number (0:1) [Hex Flash TYPE / SIZE External Tool T/ECOM - PowerQUICC II Communication tool Reserved T1 Circuit Emulation Tool Reserved Tool Non Existent PowerQUICC II Board Version PowerQUICC IIFADS-ZU Reserved MPC8272ADS PowerQUICC II7e ADS PowerQUICC II Board Revision ENG (Engineering) PILOT Reserved MPC8272ADS User Guide A ...
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Table 5-15. External Tool Revision Encoding TOOLREV(0:3) [hex 5.11.4 BCSR3 Board Control - Status Register 3 BCSR3 is a control register which is accessed at offset 0xC from the BCSR base address. Its a read- write register ...
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... Table 5-18. PCI Board Present Signal Definitions PCIx_PRSNT (0:1) [Hex] 1 Provided that BCSR is not disabled. Function Table 5-17. BCSR4 Description Function Expansion Configuration 0 Expansion board present, 7.5W maximum 1 Expansion board present, 25W maximum MPC8272ADS User Guide PON DEF 1 . BCSR4s’ various fields are PON DEF ATT ...
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... Host Media Adaptor Figure 5-10. Debug Station Connection Schemes To support debug station connection to the COP/JTAG port pin generic header connector is provided on the MPC8272ADS, carrying the COP/JTAG signals as well as 1 Not provided with the MPC8272ADS. Expansion Configuration Expansion board present, 15W maximum ...
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... PowerQUICC II on the rising edge of TCK. This line is pulled up internally by the PowerQUICC II. I Test port Reset (L). When this signal is active (Low), it resets the JTAG logic. This line is pull-down on the MPC8272ADS with a 1KΩ resistor, to provide constant reset of the JTAG logic. O Quiescent Request (L). When asserted (low), this line indicates that the PowerQUICC II desires to enter low-power mode ...
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... This line may be driven by the PowerQUICC II as well during soft-reset sequence, for 512 system clocks. This line is pulled up on the MPC8272ADS with a 1KΩ resistor. When driven externally, it MUST be driven with an Open Drain gate. Failure in doing so might result in permanent damage to the PowerQUICC II and / or to board logic ...
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... COP/JTAG Port MPC8272ADS User Guide ...
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... This chapter explains memory mapping in the MPC8272ADS. 6.1 Overview All accesses to MPC8272ADS memory slaves are controlled by the MPC8272 memory controller. Therefore, the memory map is reprogrammable to suit the user. After the debug station performs hard reset, the debugger checks for existence, size, delay and type of the ...
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... Overview Table 6-1. MPC8272ADS Memory Map Address Memory Range Type 1 04500000 - BCSR(0:7) 04507FFF 04500000 - BCSR0 04507FE3 04500004 - BCSR1 04507FE7 04500008 - BCSR2 04507FEB 0450000C - BCSR3 04507FEF 04500010 - BCSR4 04507FF3 04500014 - BCSR5 04507FF7 04500018 - BCSR6 04507FFB 0450001C - BCSR7 04507FFF 04508000 - Empty space 045FFFFF 04600000 - ATM UNI proc ...
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... Initially at h0F000000 - h0F00FFFF, set by hard reset configuration. 4 Refer to the MPC8272 PowerQUICC II map Kbyte device is used (16 Kbyte and 32 Kbyte devices can also be used appears repeatedly in 8Kbyte multiples starting from C2000000. 6 Set by hard-reset configuration. Table 6-2. MPC8272ADS Memory Map Address Memory Range Type 00000000 - SDRAM DIMM 03FFFFFF 04000000 - ...
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... Overview Table 6-2. MPC8272ADS Memory Map Address Memory Range Type 04500000 - 1 BCSR(0:7) 04507FFF 04500000 - BCSR0 04507FE3 04500004 - BCSR1 04507FE7 04500008 - BCSR2 04507FEB 0450000C - BCSR3 04507FEF 04500010 - BCSR4 04507FF3 04500014 - BCSR5 04507FF7 04500018 - BCSR6 04507FFB 0450001C - BCSR7 04507FFF 04508000 - Empty space 045FFFFF 04600000 - ATM UNI proc ...
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... An 8-Kbyte device is used (16- and 32-Kbyte devices can also be used appears repeatedly in 8 Kbyte multiples starting from FFF00000. 6.2 PowerQUICC II Register Programming The PowerQUICC II provides the following functions on the MPC8272ADS: • System functions that include the following: — PPC bus SDRAM controller — Chip-select generator • ...
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... PCI, PCI is boot master, AP(1;3) configured as BNKSEL(0:2), APE configured as IRQ7 and CS11 as CS11 CS10 configured as BCTL1 . Family Reference Manual when it is assigned to CS0) ( Description 2 PROM Power On Reset Configuration Description Bit Boot size, Exceptions vectored to 0xFFFxxxxx, Internal MPC8272ADS User Guide 2 PROM . The two configurations are . 1 1 ...
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... Memory Controller Register Programming The memory controller on the MPC8272ADS is initialized to 100MHz operation, that is, the registers’ programming is based on 100-MHz timing calculation. It also works for slower bus speeds, but the timing must be optimized). The two possible initialization for the memory controller are the following: • ...
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... KByte block size, all types access, 1 w.s. PPC 00000041 Base bit port size, no parity, SDRAM machine 1 FE002EC0 32MByte block size, 4 banks per device, row starts at A7, 12 row lines, internal bank interleaving allowed, normal AACK operation MPC8272ADS User Guide Description 2 PROM as Boot Device Description ...
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Table 6-7. Memory Controller Initialization For 100MHz—E Reg. Device Type BR4 SM73228XG1JHBG0 by Smart Modular Tech. SM73248XG2JHBG0 by Smart Modular Tech. ASM73288XG4JHBG0 by Smart Modular Tech. OR4 SM73228XG1JHBG0 by Smart Modular Tech. SM73248XG2JHBG0 by Smart Modular Tech. SM73288XG4JHBG0 by Smart ...
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... PowerQUICC II Register Programming MPC8272ADS User Guide ...
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... DDH • V (Internal Logic) DDL • VCCSYN (CPM PLL) • VCCSYN1 (core PLL) The MPC8272ADS (see Figure 7-1) has the following power rails on it: • VCC (5V) rail • Stand By (5V) rail • V3.3 (3.3V) rail • V (1.7V-2.5V) rail DDL • +12 V rail ...
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... ATX Power Supply Figure 7-1. MPC8272ADS Power Scheme To support off-board application development, the power buses are connected to the expansion connectors so that external logic may be powered directly from the board. The maximum current allowed to be drawn from the board on each bus also depends on the current drawn by the PCI bus ...
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... Rail Some of the MPC8272ADS peripherals (not including the PCI add-in cards that should be 3.3 V only on the PCI interface, but can use 5 V for other components on-board) reside on the 5-V bus. Because the MPC8272 is not 5-V tolerant, buffering is provided between 5V peripherals and the MPC8272, protecting the MPC8272 from the higher voltage level ...
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... The ATX power connector is a 20-lead, standard ATX power connector. The female part is soldered to the PCB and the plug is connected to the power supply to facilitate fast connection or disconnection of power. 7.2.2 Fast Ethernet Port Connectors The Ethernet connector on the MPC8272ADS is a twisted-pair (100/10-Base-T) connector. Use is done with 90 RJ45-8 connector. 0 MPC8272ADS User Guide ...
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ATM 155 Port Connection The ATM 155 I/F to the media is optical rather than electrical. Use is done with HP’s HFBR 5805 optical I/F, which is placed on the edge of the board for convenient connection. 7.2.4 RS232 ...
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... The parallel connector is a standard 25 pin D-Type male connector. 7.3 PCB Layout The MPC8272ADS layout was done for high-frequency operation and follows the PCI standard layout recommendations closely. The following list of measures are taken to meet this design goal: • Traces as short as possible • ...
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... This chapter provides all information needed for support, maintenance and connectivity to the MPC8272ADS. 8.1 Interconnect Signals The MPC8272ADS interconnects with external devices by using the following set of connectors: 1. P13—RS232 ports 1 and 2 2. P16, P19—USB connectors 3. P10 and P23—100 / 10 - Base-T Ethernet ports 4. P21— ...
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... Twisted-pair receive data positive input to the MPC8272ADS 4 N.C. Not connected, Bob Smith terminated on the MPC8272ADS 5 6 TPRX~ Twisted-pair receive data negative input to the MPC8272ADS 7 N.C. Not connected, Bob Smith terminated on the MPC8272ADS 8 8.1.3 P21—COP/JTAG Connector P21 is a Motorola standard COP / JTAG connector for the 60X processors family pin-protected header connector as described in Table 8-3. Table 8-3. P16— ...
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Table 8-3. P16—COP/JTAG Connector (continued) Pin No. Signal Name Attribute 4 TRST# 5 QREQ# 6 3v3 7 TCK 8 N.C. 9 TMS 10 GND 11 SRESET# 12 GND 13 HRESET# 14 N.C. 15 XBR3# (CKSTOP_OUT#) 16 GND I Test port ...
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... I/O, T.S ATM Multi-PHY Tx Address 4. When the ATM port Multi-PHY function is enabled, this line is connected to the transmit PHY Address of the PM5384 ATM UNI. When this port is disabled, this signal is tristated and may be used for any available function of PD19. MPC8272ADS User Guide Description ...
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Table 8-4. P1—CPM Expansion Connector (continued) Pin No. Signal Name Attribute A14 ATMRXADR4(PD18) A15 ATMRXPTY (PD17) A16 ATMTXPTY (PD16) A17 I2CSDA(PD15) A18 I2CSCL(PD14) A19 A20 A21 A22 A23 A24 A25 ATMTXADR3(PD7) A26 A27 A28 A29 ATMRCLKDIS A30 EXPVCC A31 A32 ...
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... PowerQUICC II when an error is discovered in the transmit data stream. When the port is operation at 100 Mbps, the DM9161 responds by sending invalid code symbols on the line. When the Ethernet port is disabled, this line may be used for any available function of PA29. MPC8272ADS User Guide Description ...
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Table 8-4. P1—CPM Expansion Connector (continued) Pin No. Signal Name Attribute B4 ATMRXEN# (PA28) FETH1TXEN (PA28) B5 ATMRSOC (PA27) FETH1RXDV (PA27) B6 ATMRCA (PA26) FETH1RXER (PA26) I/O, T.S. ATM Receive Enable (L). When this signal is asserted (Low), while the ...
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... ATMRFCLK When the ATM port is disabled, these lines are tristated and may be used for any available respective function. I/O, T.S. PowerQUICC II’s Port A (9:0). Parallel I/O or dedicated CPM lines. May be used for any of their available functions. MPC8272ADS User Guide Description 3 . ...
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Table 8-4. P1—CPM Expansion Connector (continued) Pin No. Signal Name Attribute PC26 B30 B31 B32 PB27 PB26 C6 PB25 C7 PB24 C8 C9 RS_RXD2 (PD22) C10 RS_TXD2 (PD21) PC9 C11 PD20 C12 C13 C14 FETH1RXDV ...
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... Enabled only when pin A29 of this connector is either not connected or driven low. Otherwise, Tri-stated. Digital Ground. Connected to main GND plane of the ADS. O PowerQUICC II’s Port C (31:22) Parallel I/O lines. May be used to I/O, T.S. any of their available functions. MPC8272ADS User Guide Description ...
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Table 8-4. P1—CPM Expansion Connector (continued) Pin No. Signal Name Attribute PC25 D7 USBCLK D8 D9 RS_CD1# (PC23) FETH1TXCK (PC22) D10 ATMTFCLK (PC21) D11 FETH1RXCK (PC21) USBOE (PC20) D12 D13 D14 FETH2RXCK (PC17) D15 USB Clock Line. When the USB ...
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... RS232 Port 2 Carrier Detect (L). Connected via RS232 transceiver to RS232 DTR2# input, allowing detection of a connected terminal to this port. This line is simply a PI/O input line to the PowerQUICC II. When RS232 Port 2 is disabled, this line is tristated and may be used for any available function of PC8. MPC8272ADS User Guide Description ...
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Table 8-4. P1—CPM Expansion Connector (continued) Pin No. Signal Name PC1 D31 PC0 D32 1 The functions in parenthesis, are PowerQUICC II’s parallel I/Os. 2 For that matter, both 100-Base-T and 10-Base-T. 3 Normally connected to ATMTFCLK on the ADS. ...
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... AD[30] +3.3V AD[28] AD[26] Ground AD[24] IDSEL +3.3V AD[22] AD[20] Ground AD[18] AD[16] +3.3V FRAME# Ground TRDY# Ground STOP# Not Connected +3.3V SDONE MPC8272ADS User Guide Comments Not Connected 3.3 volt key 3.3 volt key Not Connected Not Connected Not Connected ...
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Table 8-5. P26, P28, P29 Pin Side B Number 41 +3.3V 42 SERR# 43 +3.3V 44 C/BE[1]# 45 AD[14] 46 Ground 47 AD[12] 48 AD[10] 49 M66EN 50 Ground 51 Ground 52 AD[08] 53 AD[07] 54 +3.3V 55 AD[05] 56 ...
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... O ISP transmit data output. This the prog. logic’s JTAG serial data output driven by falling edge of TCK. O Digital GND. Main GND plane. - Not connected - Not connected MPC8272ADS User Guide Signal -12VDC Groung Power_On Groung Groung Groung -5VDC +5VDC ...
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P2—System Expansion Connector 128-pin DIN 41612 connector that provides a minimal system I/F required to interface various types of communication transceivers. This connector contains 16-bit (lower PPC bus) address lines, 16-bit (higher PPC ...
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... KΩ resistors. See also Table 10-38. "BCSR2 Description" on page 23 - Not connected O 3.3V Power Out. These lines are connected to the main 3.3V plane of the PowerQUICC IIPCIAI-ADS, this, to provide 3.3V power where necessary for external tool connected. MPC8272ADS User Guide Description 1 :3). These lines should be driven by ...
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Table 8-8. P2 Pin No. Signal Name Attribute B25 N.C. B26 EXPVCC B27 B28 B29 B30 B31 B32 C1 GND C2 CLK8 C3 GND C4 BTOOLCS1# C5 BTOOLCS2# C6 GND C7 ATMEN# C8 ATMRST# C9 FETHRST# C10 HRESET# C11 ...
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... D(0:15) lines is controlled by on-board logic. These lines are driven only if BTOOLCS1# or BTOOLCS2# are asserted. Otherwise they are tristated. The direction of these lines is determined by buffered BCTL0, in function of W/R#. - Not connected O Digital ground. Connected to main GND plane of the ADS. MPC8272ADS User Guide Description ...
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Table 8-8. P2 Pin No. Signal Name Attribute D4 EXPWE0# D5 EXPWE1# D6 GND D7 EXPGL0# D8 EXPGL1# D9 EXPGL2# D10 EXPGL3# D11 EXPGL4# D12 EXPGL5# D13 GND D14 EXPALE D15 EXPCTL0 System Expansion Connector (continued) O Expansion Write ...
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... System Expansion Connector (continued) Attribute O Digital Ground. Connected to main GND plane of the ADS. — USB Connectors Signal Name Description 5V Power Power line of the USB cable D- Twisted-pair transmit data negative D+ Twisted-pair receive data positive GND Ground connection MPC8272ADS User Guide Description ...
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... The two programmable logic devices on board are the following BCSR and PCI interrupt controller Power switch debounce 8.2.1 U3—BCSR Code MODULE MPC8272ADS_BCSR TITLE 'MPC8272ADS control status register' "****************************************************************************** "* This file (Prototype) is based on the PQ2FADS-VR (08/21/03): "****************************************************************************** "****************************************************************************** "* In this file (Prototype) the following changes were made (03/06/03): " ...
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... Ethernet 1/2 Off to disable MDIO/MDC FEth1PLLOn_B PIN 131 ; " FEth1 TxCLK clock buffer PLL On for 100Base-T MII1PLLOff_B PIN 129istype'com' ; " FEth1 TxCLK buffer PLL Off - 10Base-T FEth2PLLOn_B PIN 127 ; " FEth2 TxCLK clock buffer PLL On for 100Base-T MPC8272ADS User Guide ...
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MII2PLLOff_B PIN 117istype'com' ; " FEth2 TxCLK buffer PLL Off - 10Base-T RS232En1_B PIN 32istype 'reg,buffer' ; " RS232 port 1 enable RS232Dis1_B PIN 56istype 'com' ; " RS232 port 1 Disable RS232En2_B PIN 3istype 'reg,buffer' ; " RS232 port ...
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... HardResetEnNODE istype 'com' ; " enables T.S. hard reset pin SoftResetEnNODE istype 'com' ; " enables T.S. soft reset pin "****************************************************************************** "* data buffers enable. "****************************************************************************** SyncHardReset_B NODE istype 'reg,buffer' ; " synchronized hard reset DSyncHardReset_B NODE istype 'reg,buffer' ; " double synchronized hard reset HoldOffCnt2, MPC8272ADS User Guide ...
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HoldOffCnt1, HoldOffCnt0 NODE istype 'reg,buffer' ; " data buf en hold-off counter HoldOffTc NODE istype 'com' ; " terminal count for that counter "****************************************************************************** "* Power On Reset "****************************************************************************** S_PORIn_B NODE istype 'reg,buffer' ; " synced pon reset. "****************************************************************************** "* ...
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... Data = [D0..D7] ; DataPCI = [D0..D11] ; ContReg = [SignaLamp0_B, SignaLamp1_B, AtmEn_B, AtmRst_B, AtmSinglePHY_B, FEthEn1_B, FEthRst1_B, FEthEn2_B, FEthRst2_B, RS232En1_B, RS232En2_B, USBEn_B, USBHiSpd_B, USBVccO] ; ReadBcsr0 = [ SignaLamp0_B, SignaLamp1_B] ; ReadBcsr1 = [bcsrConfEn, boot_device_B, AtmEn_B, AtmRst_B.fb, FEthEn1_B, FEthRst1_B.fb, RS232En1_B, RS232En2_B] ; ReadBcsr3 = [USBEn_B, USBHiSpd_B, USBVccO, FEthEn2_B, FEthRst2_B.fb, 0, AtmSinglePHY_B, MPC8272ADS User Guide ...
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PCI_Mode_B]; DrivenContReg = [SignaLamp0_B, SignaLamp1_B, AtmEn_B, AtmSinglePHY_B, FEthEn1_B, FEthEn2_B, RS232En1_B, RS232En2_B, USBEn_B] ; " USBVccO] ; ClockedContReg = [SignaLamp0_B, SignaLamp1_B, AtmEn_B, AtmRst_B, AtmSinglePHY_B, FEthEn1_B, FEthEn2_B, FEthRst1_B, FEthRst2_B, RS232En1_B, RS232En2_B, USBEn_B, USBHiSpd_B, USBVccO] ; IntReg = [Slot0IntA, Slot0IntB, Slot0IntC, Slot0IntD, Slot1IntA, ...
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... VGR_READ_BCSR_3 = (!BrdContRegCs_B & !R_B_W & !A27 & A28 & A29) ; VGR_READ_BCSR_4 = (!BrdContRegCs_B & !R_B_W & A27 & !A28 & !A29) ; "****************************************************************************** "****************************************************************************** "* BCSR 0 definitions. "****************************************************************************** "****************************************************************************** SIGNAL_LAMP_ON = 0 ; "*********************************************** "******* Power On Defaults Assignments "*********************************************** SIGNAL_LAMP0_PON_DEFAULT = !SIGNAL_LAMP_ON ; SIGNAL_LAMP1_PON_DEFAULT = !SIGNAL_LAMP_ON ; MPC8272ADS User Guide ...
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Data Bits Assignments "******************************************* SIGNAL_LAMP0_DATA_BIT = [D6] ; SIGNAL_LAMP1_DATA_BIT = [D7] ; "****************************************************************************** "****************************************************************************** "* BCSR 1 definitions. "****************************************************************************** "****************************************************************************** BCSR_BOOT = 0 ;" bcsrConfEn = 0 Hard Reset Conf Word from BCSR MEMORY_BOOT = 1 ;" bcsrConfEn ...
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... Slot1IntD # " Slot2IntA # " Slot2IntB # " Slot2IntC # " Slot2IntD) ; "****************************************************************************** "****************************************************************************** "* PCI Interrupt Register definitions. "****************************************************************************** "****************************************************************************** Slot0IntA_Active = 1 ; " PCI Slot 0 Interrupt A asserted Slot0IntB_Active = 1 ; " PCI Slot 0 Interrupt B asserted Slot0IntC_Active = 1 ; " PCI Slot 0 Interrupt C asserted [D3] ; [D4] ; MPC8272ADS User Guide ...
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Slot0IntD_Active = 1 ; " PCI Slot 0 Interrupt D asserted Slot1IntA_Active = 1 ; " PCI Slot 1 Interrupt A asserted Slot1IntB_Active = 1 ; " PCI Slot 1 Interrupt B asserted Slot1IntC_Active = 1 ; " PCI Slot ...
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... SM73228XU1 = (F_PD == 2) ; " MByte bank SM73248XU2 = (F_PD == 1) ; " MByte banks SM73288XU4 = (F_PD == 0) ; " MByte banks FLASH_BANK1 = ( CP29020 # SM73228XU1 # (SM73248XU2 & !A8) # (SM73288XU4 & !A7 & !A8 FLASH_BANK2 = ( (SM73248XU2 & A8) # (SM73288XU4 & !A7 & A8 FLASH_BANK3 = ( A7 & !A8 & SM73288XU4 ) ; FLASH_BANK4 = ( A7 & A8 & SM73288XU4 ) ; "****************************************************************************** MPC8272ADS User Guide ...
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ATM UNI Declarations. "****************************************************************************** "****************************************************************************** "* Reset Declarations. "****************************************************************************** HARD_RESET_ACTIVE = 0 ; SOFT_RESET_ACTIVE = 0 ; HARD_RESET_ASSERTED = (SyncHardReset_B.fb == HARD_RESET_ACTIVE) ; "****************************************************************************** "* data buffers enable. "****************************************************************************** BUFFER_DISABLED = 1 ; BUFFER_ENABLED = !BUFFER_DISABLED ; BUFFER_HOLD_OFF = ...
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... SignaLamp1_B state SIGNAL_LAMP_ON: if (VGR_WRITE_BCSR_0 & (SIGNAL_LAMP1_DATA_BIT.pin == !SIGNAL_LAMP_ON) & (!PON_RESET # (SIGNAL_LAMP1_PON_DEFAULT != SIGNAL_LAMP_ON)) # (PON_RESET & (SIGNAL_LAMP1_PON_DEFAULT == !SIGNAL_LAMP_ON)) ) then !SIGNAL_LAMP_ON else SIGNAL_LAMP_ON ; state !SIGNAL_LAMP_ON: if (VGR_WRITE_BCSR_0 & (SIGNAL_LAMP1_DATA_BIT.pin == SIGNAL_LAMP_ON) & (!PON_RESET # (SIGNAL_LAMP1_PON_DEFAULT != !SIGNAL_LAMP_ON)) # (PON_RESET & (SIGNAL_LAMP1_PON_DEFAULT == SIGNAL_LAMP_ON)) ) then * MPC8272ADS User Guide ...
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SIGNAL_LAMP_ON else !SIGNAL_LAMP_ON ; "****************************************************************************** "****************************************************************************** "* BCSR1 State Machines "****************************************************************************** "****************************************************************************** state_diagram AtmEn_B state ATM_ENABLED: if (VGR_WRITE_BCSR_1 & (ATM_ENABLE_DATA_BIT.pin == !ATM_ENABLED) & (!PON_RESET # (ATM_ENABLE_PON_DEFAULT != ATM_ENABLED)) # (PON_RESET & (ATM_ENABLE_PON_DEFAULT == !ATM_ENABLED)) ) then !ATM_ENABLED else ATM_ENABLED ; ...
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... RS232_2_ENABLE)) # (PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == !RS232_2_ENABLE)) ) then !RS232_2_ENABLE else RS232_2_ENABLE ; state !RS232_2_ENABLE: if (VGR_WRITE_BCSR_1 & (RS232_2_ENABLE_DATA_BIT.pin == RS232_2_ENABLE) & (!PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != !RS232_2_ENABLE)) # (PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == RS232_2_ENABLE)) ) then RS232_2_ENABLE else !RS232_2_ENABLE ; "****************************************************************************** "****************************************************************************** "* BCSR3 State Machines MPC8272ADS User Guide ...
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USBEn_B state USB_ENABLED: if (VGR_WRITE_BCSR_3 & (USB_ENABLE_DATA_BIT.pin == !USB_ENABLED) & (!PON_RESET # (USB_ENABLE_PON_DEFAULT != USB_ENABLED)) # (PON_RESET & (USB_ENABLE_PON_DEFAULT == !USB_ENABLED)) ) then !USB_ENABLED else USB_ENABLED ; state !USB_ENABLED: if (VGR_WRITE_BCSR_3 & (USB_ENABLE_DATA_BIT.pin == USB_ENABLED) & (!PON_RESET ...
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... ATM_SINGLE_PHY_ENABLED)) # (PON_RESET & (ATM_SINGLE_PHY_ENABLE_PON_DEFAULT == !ATM_SINGLE_PHY_ENABLED)) ) then !ATM_SINGLE_PHY_ENABLED else ATM_SINGLE_PHY_ENABLED ; state !ATM_SINGLE_PHY_ENABLED: if (VGR_WRITE_BCSR_3 & (ATM_SINGLE_PHY_ENABLE_DATA_BIT.pin == ATM_SINGLE_PHY_ENABLED) & (!PON_RESET # (ATM_SINGLE_PHY_ENABLE_PON_DEFAULT != !ATM_SINGLE_PHY_ENABLED)) # (PON_RESET & (ATM_SINGLE_PHY_ENABLE_PON_DEFAULT == ATM_SINGLE_PHY_ENABLED)) ) then ATM_SINGLE_PHY_ENABLED else !ATM_SINGLE_PHY_ENABLED ; "****************************************************************************** equations AtmMultiPHY_B = !AtmSinglePHY_B ; MPC8272ADS User Guide ...
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USBDis_B = !USBEn_B ; USBLowSpd_B = !USBHiSpd_B ; USBVccOut = !USBVccO ; FEthDis1_B = !FEthEn1_B ; FEthDis2_B = !FEthEn2_B ; RS232Dis1_B = !RS232En1_B ; RS232Dis2_B = !RS232En2_B ; FCC1On_B = FEthEn1_B & AtmEn_B ; FCC1Off_B = !FCC1On_B ; MIIOn_B = ...
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... Slot0IntD_Active else !Slot0IntD_Active ; "****************************************************************************** state_diagram Slot1IntA state Slot1IntA_Active ((HardReset_B == 0) & (Slot1IntA_PON_DEFAULT == !Slot1IntA_Active)) # (!(HardReset_B == 0) & ((PCI_INTD_B & !Slot1IntAMask.fb) # Slot1IntAMask.fb)) ) then !Slot1IntA_Active else Slot1IntA_Active ; state !Slot1IntA_Active ((HardReset_B == 0) & (Slot1IntA_PON_DEFAULT == Slot1IntA_Active)) # (!(HardReset_B == 0) & !PCI_INTD_B & !Slot1IntAMask.fb) ) then Slot1IntA_Active MPC8272ADS User Guide ...
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Slot1IntB state Slot1IntB_Active ((HardReset_B == 0) & (Slot1IntB_PON_DEFAULT == !Slot1IntB_Active)) # (!(HardReset_B == 0) & ((PCI_INTA_B & !Slot1IntBMask.fb) # Slot1IntBMask.fb)) ) then !Slot1IntB_Active else Slot1IntB_Active ; state !Slot1IntB_Active ((HardReset_B == 0) ...
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... Slot2IntC_Active else !Slot2IntC_Active ; "****************************************************************************** state_diagram Slot2IntD state Slot2IntD_Active ((HardReset_B == 0) & (Slot2IntD_PON_DEFAULT == !Slot2IntD_Active)) # (!(HardReset_B == 0) & ((PCI_INTB_B & !Slot2IntDMask.fb) # Slot2IntDMask.fb)) ) then !Slot2IntD_Active else Slot2IntD_Active ; state !Slot2IntD_Active ((HardReset_B == 0) & (Slot2IntD_PON_DEFAULT == Slot2IntD_Active)) # (!(HardReset_B == 0) & !PCI_INTB_B & !Slot2IntDMask.fb) ) then MPC8272ADS User Guide ...
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Slot2IntD_Active else !Slot2IntD_Active ; "****************************************************************************** "****************************************************************************** "* PCI Interrupt Mask Register "****************************************************************************** "****************************************************************************** equations IntMaskReg.clk = SYSCLK ; IntMaskReg. IntMaskReg. "****************************************************************************** state_diagram Slot0IntAMask state Slot0IntAMask_Active: if (VGR_WRITE_IntMaskReg & (Slot0IntAMask_DATA_BIT.pin == !Slot0IntAMask_Active) & (!(HardReset_B == ...
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... Slot1IntAMask_Active ; state !Slot1IntAMask_Active: if (VGR_WRITE_IntMaskReg & (Slot1IntAMask_DATA_BIT.pin == Slot1IntAMask_Active) & (!(HardReset_B == 0) # (Slot1IntAMask_PON_DEFAULT == Slot1IntAMask_Active)) # ((HardReset_B == 0) & (Slot1IntAMask_PON_DEFAULT == Slot1IntAMask_Active)) ) then Slot1IntAMask_Active else !Slot1IntAMask_Active ; "****************************************************************************** state_diagram Slot1IntBMask state Slot1IntBMask_Active: if (VGR_WRITE_IntMaskReg & MPC8272ADS User Guide ...
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Slot1IntBMask_Active ; state !Slot1IntBMask_Active: if (VGR_WRITE_IntMaskReg & (Slot1IntBMask_DATA_BIT.pin == Slot1IntBMask_Active) & (!(HardReset_B == 0) # (Slot1IntBMask_PON_DEFAULT == ...
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... Slot2IntCMask_Active: if (VGR_WRITE_IntMaskReg & (Slot2IntCMask_DATA_BIT.pin == !Slot2IntCMask_Active) & (!(HardReset_B == 0) # (Slot2IntCMask_PON_DEFAULT == !Slot2IntCMask_Active)) # ((HardReset_B == 0) & (Slot2IntCMask_PON_DEFAULT == !Slot2IntCMask_Active)) ) then !Slot2IntCMask_Active else Slot2IntCMask_Active ; state !Slot2IntCMask_Active: if (VGR_WRITE_IntMaskReg & (Slot2IntCMask_DATA_BIT.pin == Slot2IntCMask_Active) & (!(HardReset_B == 0) # (Slot2IntCMask_PON_DEFAULT == Slot2IntCMask_Active)) # ((HardReset_B == 0) & (Slot2IntCMask_PON_DEFAULT == Slot2IntCMask_Active)) ) then Slot2IntCMask_Active else !Slot2IntCMask_Active ; "****************************************************************************** state_diagram Slot2IntDMask MPC8272ADS User Guide ...
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Slot2IntDMask_Active: if (VGR_WRITE_IntMaskReg & (Slot2IntDMask_DATA_BIT.pin == !Slot2IntDMask_Active) & (!(HardReset_B == 0) # (Slot2IntDMask_PON_DEFAULT == !Slot2IntDMask_Active)) # ((HardReset_B == 0) & (Slot2IntDMask_PON_DEFAULT == !Slot2IntDMask_Active)) ) then !Slot2IntDMask_Active else Slot2IntDMask_Active ; state !Slot2IntDMask_Active: if (VGR_WRITE_IntMaskReg & (Slot2IntDMask_DATA_BIT.pin == Slot2IntDMask_Active) & (!(HardReset_B ...
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... TransRst. ;" transceivers' reset, always enabled. !AtmRstOut_B = !AtmRst_B.fb # !HardReset_B ; !FEthRstOut1_B = !FEthRst1_B.fb # !HardReset_B ; !FEthRstOut2_B = !FEthRst2_B.fb # !HardReset_B ; "****************************************************************************** "* Hard reset configuration "****************************************************************************** "equations "RstConf_B. "RstConf_B = L; "****************************************************************************** "* NMI generation "****************************************************************************** equations NMI_B.oe = NMIEn ; NMI_B = 0 ;" O.D. " Reset push-button debouncer " Abort push-button debouncer MPC8272ADS User Guide ...
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NMIEn = !RstDeb1.com & AbrDeb1.com ;" only abort button depressed "****************************************************************************** "* local data buffers enable "****************************************************************************** equations SyncHardReset_B.clk = SYSCLK ; SyncHardReset_B. SyncHardReset_B. DSyncHardReset_B.clk = SYSCLK ; DSyncHardReset_B. DSyncHardReset_B. SyncHardReset_B := ...
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... CS4_ASSERTED & (HRESET_BOOT_IN_FLASH # BOOT_IN_FLASH) ; "****************************************************************************** "* ATM UNI Chip Select "****************************************************************************** equations AtmUniCsOut_B. !AtmUniCsOut_B = !AtmUniCsIn_B; "****************************************************************************** "* Power On Reset "****************************************************************************** equations S_PORIn_B.clk = SYSCLK ; S_PORIn_B. S_PORIn_B. S_PORIn_B := PORIn_B ; "****************************************************************************** "****************************************************************************** "* Generating Interrupt Request to the PQ2. "****************************************************************************** "****************************************************************************** equations PCI_Interrupt = (Slot0IntA # MPC8272ADS User Guide ...
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Slot0IntB # Slot0IntC # Slot0IntD # Slot1IntA # Slot1IntB # Slot1IntC # Slot1IntD # Slot2IntA # Slot2IntB # Slot2IntC # Slot2IntD) ; PCI_IRQ_B.oe = PCI_Interrupt ; " Open-Drain output !PCI_IRQ_B = PCI_Interrupt ; " Interrupt Request shows after OE "****************************************************************************** ...
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... NODE istype 'reg,buffer' ; "****************************************************************************** "****************************************************************************** .X., . .C., .D., .U. ; "****************************************************************************** "* SIMULATION = 1 ; "****************************************************************************** "* Signal groups "****************************************************************************** counter = [counter7,counter6,counter5,counter4, counter3,counter2,counter1,counter0] ; countera = [countera7,countera6,countera5,countera4, countera3,countera2,countera1,countera0] ; counterb = [counterb7,counterb6,counterb5,counterb4, counterb3,counterb2,counterb1,counterb0] ; "****************************************************************************** "* ATX Power Declarations. "****************************************************************************** MPC8272ADS User Guide ...
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PowerOn = 0 ; PowerOff = 1 ; "****************************************************************************** "* Equations, state diagrams. "****************************************************************************** "****************************************************************************** "****************************************************************************** equations "****************************************************************************** "****************************************************************************** "* Generating PowerOn signal to the ATX Power Supply. "****************************************************************************** "****************************************************************************** equations inv1 = !inv5.com ;" generating internal clock oscilator inv2 ...
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... Programmable Logic Equations MPC8272ADS User Guide ...
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... This appendix provides a list of the major differences between revisions of the MPC8272ADS User Guide. A.1 Revision Changes From Revision 0 to Revision 0.1 Changes to the MPC8272ADS User Guide from Revision 0 to Revision 0.1 are as follows: Section, Page Throughout manual Changes Non-technical reformatting. In addition, an index was added. ...
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... Appendixes MPC8272ADS User Guide MOTOROLA ...
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Numerics -12V indicator, 4-4 12V indicator, 4-4 3.3-V indicator, 4-4 3IDDL Measurement, 4-2 5-V indicator, 4-4 60X bus mode, 1-2 A abbreviations, xvii ABORT interrupt, 5-9 ABORT Switch, 4-1 acronyms, xvii add-in cards, 7-2, 7-3, 7-5 ATM ON indicator, 4-5 ...
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... LINK indicator, 4-7 transceivers, 5-9 external debugger connection indicator, 4-7 F Fast Ethernet ports, 4-5 Flash memory access time provided with MPC8272ADS, 5-17 demonstration tool, 1-1 installation module on MPC8272ADS, 3-4 programming voltage, 5-19 SIMM, 2-5, 6-1 SIMM Installation, 3-4 stand alone operation, 3-2 ...
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... PPC bus SDRAM controller, 6-5 precharge-all command, 5-16 programmable logic equations, 8-23 R register programming, 6-5 Reset Configuration Switch, 4-2 reset sources on the MPC8272ADS, 5-1 revision history of this document, A-1 RP1 rotation direction, 2-3 RS232 connection, 3-3 port, 4-5 serial port connector, 3-3 ...
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... UTOPIA multi PHY indicator, 4-4 V VDDH rail, 7-3 VDDL bus, 7-3 indicator, 4-7 trimmer, 2-3 voltage supply level, 2-3 voltage changing core logic of the MPC8272, 7-3 internal logic operation, 1-3 VPP source selector, 4-3 MPC8272ADS User Guide ...