MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 103

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin No.
B4
B5
B6
FETH1RXDV (PA27)
FETH1RXER (PA26)
FETH1TXEN (PA28)
ATMRXEN# (PA28)
ATMRSOC (PA27)
ATMRCA (PA26)
Signal Name
Table 8-4. P1—CPM Expansion Connector (continued)
Attribute
I/O, T.S.
I/O, T.S.
I/O, T.S.
I/O, T.S.
I/O, T.S.
I/O, T.S.
Chapter 8. Support
ATM Receive Enable (L). When this signal is asserted (Low), while
the ATM port is enabled and ATMRFCLK
data is available at the PM5384’s ATMRXD(7:0) lines.
When negated while ATMRFCLK goes high data on ATMRXD(7:0)
is invalid, however driven.
When the ATM port is disabled, this line may be used for any
available function for PA28.
Fast-Ethernet 1 Transmit Enable (H). The PowerQUICC II will
assert (High) this line, to indicate data valid on the FETHTXD(3:0)
lines.
When the Fast-Ethernet port is disabled, this line may be used for
any available function of PA28.
ATM Receive Start Of Cell (H). When this signal is asserted (High),
while the ATM port is enabled, it indicates, that the 1’st octet of
data for the received cell is available at the PM5384’s
ATMRXD(7:0) lines. This line is updated over the rising edge of
ATMRFCLK.
When the ATM port is disabled, this line is tristated and may be
used for any available function for PA27.
Fast-Ethernet 1 Receive Data Valid (H). When this signal is
asserted (High) while the Fast Ethernet port is enabled and
FETHRXCK goes high, it indicates that data is valid on the MII
Receive Data lines - FETHRXD(3:0).
When the Fast Ethernet port is disabled, this line is tristated and
may be used for any available function go PA27.
ATM Receive Cell Available (H). When this signal is asserted
(High), while the ATM port is enabled and ATMRFCLK goes high,
it indicates that the PM5384’s receive FIFO is either full or that
there are 4 empty bytes left in it - PM5384 internal programming
dependent.
When the ATM port is disabled, this line is tristated and may be
used for any available function of PA26.
Fast-Ethernet 1 Receive Error (H). When this signal is asserted
(High) by the DM9161, while the Ethernet port is enabled and
FETH1RXCK goes high, it indicates that the port is receiving
invalid data symbols from the network.
When the Ethernet port is disabled, this line is tristated and may be
used for any available function of PA26.
Description
3
Interconnect Signals
goes high, on octet of