MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 79

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin No.
10
11
12
13
14
15
16
9
(CKSTOP_OUT)
Table 5-20. COP/JTAG Port Signals Description (continued)
Signal Name
SRESET
HRESET
XBR3
GND
GND
TMS
N.C.
N.C.
Attribute
I/O, O.D.
I/O, O.D.
I/O
O
O
I
-
-
Chapter 5. Module Design
Test Mode Select. This signal qualified with TCK in a same
manner as TDI, changes the state of the JTAG machine. This line
is pulled up internally by the PowerQUICC II.
Not Connected.
Soft Reset (L). This is the PowerQUICC II’s soft reset which is in
fact a non-maskable interrupt, making the PowerPC take the
reset exception from the reset vector. This line may be driven by
the PowerQUICC II as well during soft-reset sequence, for 512
system clocks. This line is pulled up on the MPC8272ADS with a
1KΩ resistor. When driven externally, it MUST be driven with an
Open Drain gate. Failure in doing so might result in
permanent damage to the PowerQUICC II and / or to board
logic.
Digital GND. Main GND plane.
PowerQUICC II’s Hard Reset (L). When asserted by an external
H/W, generates Hard-Reset sequence for the PowerQUICC II.
During that sequence, asserted by the MPC for 512 system
clocks. Pulled Up on the MPC8272ADS using a 1KΩ resistor.
When driven by an external tool, MUST be driven with an Open
Drain gate. Failure in doing so might result in permanent
damage to the PowerQUICC II and / or to board logic.
Not Connected.
Normally configured as XBR3 which has no function with this
connector. May be configured as CKSTOP_OUT - Check Stop
Out (L). When asserted (Low) indicates that the PowerQUICC II
core has entered a Check-Stop state.
Digital GND. Main GND plane.
Description
COP/JTAG Port