MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 66
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MPC8272ADS
Manufacturer Part Number
MPC8272ADS
Description
KIT DEVELOPMENT MPC8272
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheet
1.MPC8272ADS.pdf
(158 pages)
Specifications of MPC8272ADS
Contents
Board
For Use With/related Products
MPC8272
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 66 of 158
- Download datasheet (2Mb)
Communication Ports
5.10 Communication Ports
The MPC8272ADS has several communication ports, to allow convenient evaluation of the
CPM features. Obviously, it is not possible to provide all types of communication interfaces
supported by the CPM, but it is made convenient to connect any communication interface
devices to the MPC8272 via the CPM Expansion connectors, residing on the edge of the
board.
All CPM pins are visible on MICTOR connectors. In order to avoid long routes and stubs,
bus muxing devices are used to direct the CPM signals to a communication element
on-board or to the expansion connector. A signal that is used on-board, will not be visible
in the expansion connector and vise-versa. The control is done by enabling/disabling the
communication elements on-board.
The communication ports’ interfaces provided on the MPC8272ADS are listed below:
5.10.1 ATM Port
To support the MPC8272s’ ATM controller, a 155.52Mbps User Network Interface (UNI)
is provided on board, connected to FCC1 of the MPC8272 via UTOPIA I/F. Use is done
with PM5384 S/UNI-155-ULTRA by PMC-SIERA. Although these transceivers are
capable of supporting 51.84Mbps rate, support is given to 155.52Mbps only. The PHY
supports UTOPIA level 2 which means support for 8 bit UTOPIA bus in single or multi
PHY mode. The control over the mode of UTOPIA bus connection is done through BCSR3.
The control over the transceiver is done using the microprocessor interface of the
transceiver, controlled by the MPC8272 memory controllers’ GPCM.
The ATM transceiver may be enabled / disabled at any time by writing ’0’ /’1’ respectively
to the ATMEN bit in BCSRx. When ATMEN is negated, (’1’) the microprocessor control
port is also detached from the MPC8272 and its associated FCC may be used off-board via
the expansion connectors.
The ATM transceiver reset input is driven by HRESET signal of the MPC8272, so that the
UNI is reset whenever a hard-reset sequence occurs. The UNI may also be reset by either
1. 155 Mbps ATM UNI on FCC1 (switchable with Fast ethernet) with Optical
2. Two 100/10-Base-T Ports on FCC1 (switchable with ATM) and FCC2 with T.P.
3. Dual RS232 ports residing on SCC1 & SCC4.
4. USB port, 1.1 USB standard compliant, with speed control (12 or 1.5 Mbps) and
interface, using the UTOPIA Level 2 interface - support for 8 bit in multi or single
PHY.
interface, MII or RMII controlled.
mode control (Host or slave).
MPC8272ADS User Guide
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