MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 99

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin No.
10
11
12
13
14
15
16
4
5
6
7
8
9
(CKSTOP_OUT#)
Signal Name
HRESET#
SRESET#
QREQ#
TRST#
XBR3#
GND
GND
GND
TMS
TCK
N.C.
N.C.
3v3
Table 8-3. P16—COP/JTAG Connector (continued)
Attribute
I/O, O.D.
I/O, O.D.
I/O
O
O
O
O
O
I
-
I
-
I
Chapter 8. Support
Test port reset~ (L). When this signal is active (Low), it resets the
JTAG logic of the PowerQUICC II. This line is pull-down on the
ADS with a 1KΩ resistor, to provide constant reset of the JTAG
logic.
Quiescent request (L). When asserted (low), this line indicates that
the PowerQUICC II desires to enter low-power mode. This signal
may be required by a debug station.
3.3V power supply bus.
Test port clock. This clock shifts in / out data to / from the JTAG
logic. Data is driven on the falling edge of TCK and is sampled both
internally and externally on it’s rising edge.
TCK is pulled up internally by the PowerQUICC II.
Not connected.
Test Mode Select. This signal qualified with TCK in a same manner
as TDI, changes the state of the JTAG machine. This line is pulled
up internally by the PowerQUICC II.
Digital GND. Main GND plane.
Soft Reset (L). This is the PowerQUICC II’s soft reset which is in
fact a non-maskable interrupt, making the PPC take the reset
exception from the reset vector. This line may be driven by the
PowerQUICC II as well during soft-reset sequence, for 512 system
clocks. This line is pulled up on the ADS with a 1KΩ resistor. When
driven externally, it MUST be driven with an Open Drain gate.
Failure to do so may result in permanent damage to the
PowerQUICC II and / or to ADS logic.
Digital GND. Main GND plane.
PowerQUICC II’s Hard Reset (L). When asserted by an external
H/W, generates Hard-Reset sequence for the PowerQUICC II.
During that sequence, asserted by the PowerQUICC II for 512
system clocks. Pulled Up on the ADS using a 1KΩ resistor.
When driven by an external tool, MUST be driven with an Open
Drain gate. Failure to do so may result in permanent damage
to the PowerQUICC II and / or to ADS logic.
Not Connected.
Normally configured as XBR3# which has no function with this
connector. May be configured as CKSTP_OUT# - Check Stop Out
(L). When asserted (Low) indicates that the PowerQUICC II core
has entered a Check-Stop state.
Digital GND. Main GND plane.
Description
Interconnect Signals