MPC8272ADS Freescale Semiconductor, MPC8272ADS Datasheet - Page 71

• Manufacturer Part Number: MPC8272ADS
• Description: KIT DEVELOPMENT MPC8272
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8272ADS

• Contents: Board
• For Use With/related Products: MPC8272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 - 31
BIT
BIT
0-5
5.11.1 BCSR0 Board Control—Status Register 0
The BCSR0 is a control register on the MPC8272ADS. It is accessed at offset 0 from BCSR
base address. It may be read or written at any time
Power-On reset. BCSR0 fields are described in Table 5-7.
5.11.2 BCSR1 Board Control—Status Register 1
The BCSR1 is a control register on the MPC8272ADS. It is accessed at offset 4 from BCSR
base address. It may be read or written at any time
Power-On reset. The fields are described in Table 5-8
6
7
0
1
2
3
1
2
Provided that BCSR is not disabled.
Provided that BCSR is not disabled.
FLASH_CS0
MNEMONIC
MNEMONIC
GPL LED 1
GPL LED 2
Conf_Word
ATM_RST
Reserved
Reserved
ATM_EN
S
General Purpose Led 1. General purpose Led to be used by the user.
General Purpose Led 2. General purpose Led to be used by the user.
Un-implemented
Config_Source. When asserted (low) Hard Reset Configuration Word is
sourced from the BCSR. When negated, Hard Reset Configuration Word is
sourced from the FLASH/EEPROM. The assignments selection is done via
a dedicated jumper JP7.
FLASH CS0. When asserted (low) CS0 is assigned to the FLASH SIMM
and CS4 is assigned to E
E
selection is done via a dedicated jumper.
ATM Port Enable. When asserted (low) the ATM UNI chip (PM5384)
connected to FCC1 is enabled for transmission and reception. When
negated, the ATM transceiver is in standby mode, freeing all its i/f signals for
off-board use via the expansion connectors.
ATM Port Reset. When asserted (low), the ATM port transceiver is in reset
state. This line is driven also by HRESET signal of the MPC8272.
2
PROM and CS4 is assigned to the FLASH SIMM. The assignments
Table 5-7. BCSR0 Description
Table 5-8. BCSR1 Description
Chapter 5. Module Design
2
PROM. When negated, CS0 is assigned to the
Function
Function
Board Control and Status Register - BCSR
1
2
. BCSR0 gets its defaults upon
. BCSR1 gets its defaults upon
PON
PON
DEF
DEF
0
0
0
0
0
0
1
1
ATT.
R,W
R,W
ATT.
R,W
R,W
R/W
R
R
R