D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 116

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.5.2 Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs,
after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the
CPU is currently executing one of these interrupt-inhibiting instructions, however, when the
instruction is completed the CPU always continues by executing the next instruction.
5.5.3 Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests.
When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the
transfer is completed, not even NMI.
When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
5.5.4 Usage Notes
The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read
while set to 1. However, it is possible for the IRQnF flag to be cleared by mistake simply by
writing 0 to it, irrespective of whether it has been read while set to 1, with the result that interrupt
exception handling is not executed. This will occur when the following conditions are met.
1. Setting conditions
(1) Multiple external interrupts (IRQa, IRQb) are being used.
(2) Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and
(3) A bit-manipulation instruction is used on the IRQ status register for clearing the IRQaF flag,
2. Generation conditions
(1) A read of the ISR register is executed to clear the IRQaF flag while it is set to1, then the
clearing by hardware for the IRQbF flag.
or else ISR is read as a byte unit, the IRQaF flag bit is cleard, and the values read in the other
bits are written as a byte unit.
L1: EEPMOV.W
MOV.W R4,R4
BNE
L1
99