D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 31

IC H8/3002 ROMLESS 100QFP

D13002F16V

Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of D13002F16V

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 1-3 Pin Functions (cont)
Type
Refresh
controller
Symbol
RFSH
CS
RD
HWR
LWR
DREQ
DREQ
TEND
TEND
TCLKD to
TCLKA
TIOCA
TIOCA
TIOCB
TIOCB
TOCXA
TOCXB
3
1
0
1
0
4
0
4
0
,
,
4
4
to
to
FP-100B,
TFP-100B
87
88
70
71
72
9, 8
94, 93
96 to 93
4, 2, 99,
97, 95
5, 3, 100,
98, 96
6
7
Pin No.
FP-100A
89
90
72
73
74
11, 10
96, 95
98 to 95
6, 4, 1,
99, 97
7, 5, 2,
100, 98
8
9
14
I/O
Output
Output
Output
Output
Output
Input
Output
Input
Input/
output
Input/
output
Output
Output
Name and Function
Refresh: Indicates a refresh cycle
Row address strobe
strobe signal for DRAM connected to area 3
Column address strobe CAS: Column
address strobe signal for DRAM connected
to area 3; used with 2WE DRAM.
Write enable: Write enable signal for DRAM
connected to area 3; used with 2CAS DRAM.
Upper write: Write enable signal for DRAM
connected to area 3; used with 2WE DRAM.
Upper column address strobe: Column
address strobe signal for DRAM connected
to area 3; used with 2CAS DRAM.
Lower write: Write enable signal for DRAM
connected to area 3; used with 2WE DRAM.
Lower column address strobe: Column
address strobe signal for DRAM connected
to area 3; used with 2CAS DRAM.
DMA request 1 and 0: DMAC activation
requests
Transfer end 1 and 0: These signals indicate
that the DMAC has ended a data transfer
Clock input D to A: External clock inputs
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
Input capture/output compare B4 to B0:
GRB4 to GRB0 output compare or input
capture, or PWM output
Output compare XA4: PWM output
Output compare XB4: PWM output
RAS: Row address

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