D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 473

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 13-8 shows an example of SCI receive operation in asynchronous mode.
13.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set
to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 13-9 shows an example of communication among different processors using a
multiprocessor format.
Figure 13-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
RDRF
FER
1
Start
bit
0
D0
D1
1 frame
Data
D7
Parity
bit
0/1
RXI
request
Stop
bit
1
457
Start
bit
0
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
D0
D1
Data
D7
Parity
bit
0/1
Framing error,
ERI request
Stop
bit
1
Idle (mark)
state
1