D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 488
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Note: * When switching from transmitting or receiving to simultaneous
Figure 13-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
No
No
No
transmitting and receiving, clear the TE and RE bits both to 0,
then set the TE and RE bits both to 1 simultaneously.
Clear TE and RE bits to 0 in SCR
and clear RDRF flag to 0 in SSR
Start transmitting and receiving
Write transmit data in TDR and
Read receive data from RDR
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
End of transmitting and
ORER = 1?
TDRE = 1?
RDRF = 1?
receiving?
Initialize
End
Yes
No
Yes
Yes
Error handling
Yes
472
1
2
4
5
3
1.
2.
3.
4.
5.
SCI initialization: the transmit data
output function of the TxD pin and
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
SCI status check and transmit
data write: read SSR, check that
the TDRE flag is 1, then write
transmit data in TDR and clear
the TDRE flag to 0.
Notification that the TDRE flag has
changed from 0 to 1 can also be
given by the TXI interrupt.
Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the neces-
sary error handling, clear the ORER
flag to 0.
Neither transmitting nor receiving
can resume while the ORER flag
remains set to 1.
SCI status check and receive
data read: read SSR, check that
the RDRF flag is 1, then read
receive data from RDR and clear
the RDRF flag to 0. Notification
that the RDRF flag has changed
from 0 to 1 can also be given
by the RXI interrupt.
To continue transmitting and
receiving serial data: check the
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that
the TDRE flag is set to 1, indicat-
ing that data can be written, write
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
When the DMAC is activated by
a transmit-data-empty interrupt
request (TXI) to write data in TDR,
the TDRE flag is checked and
cleared automatically. When the
DMAC is activated by a receive-
data-full interrupt request (RXI) to
read RDR, the RDRF flag is
cleared automatically.
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