D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 472

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In receiving, the SCI operates as follows.
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After receiving, the SCI makes the following checks:
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of
the checks fails (receive error), the SCI operates as indicated in table 13-11.
Note: When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is
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Table 13-11 Receive Error Conditions
Receive Error
Overrun error
Framing error
Parity error
The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
internally and starts receiving.
Receive data is stored in RSR in order from LSB to MSB.
The parity bit and stop bit are received.
— Parity check:
— Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop
— Status check:
When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
not set to 1. Be sure to clear the error flags to 0.
Abbreviation
ORER
FER
PER
The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
bit is checked.
The RDRF flag must be 0 so that receive data can be transferred from
RSR into RDR.
Condition
Receiving of next data ends
while RDRF flag is still set to
1 in SSR
Stop bit is 0
Parity of receive data differs
from even/odd parity setting
in SMR
456
Data Transfer
Receive data not transferred
from RSR to RDR
Receive data transferred
from RSR to RDR
Receive data transferred
from RSR to RDR