D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 469

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In transmitting serial data, the SCI operates as follows.
•
•
•
Figure 13-6 shows an example of SCI transmit operation in asynchronous mode.
TDRE
TEND
The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
— Start bit:
— Transmit data:
— Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
— Stop bit:
— Mark state:
The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of
the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the
stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a
transmit-end interrupt (TEI) is requested at this time.
Figure 13-6 Example of SCI Transmit Operation in Asynchronous Mode
1
TXI
interrupt
request
Start
bit
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
D1
(8-Bit Data with Parity and 1 Stop Bit)
1 frame
Data
D7
Parity
bit
0/1
One 0 bit is output.
7 or 8 bits are output, LSB first.
bit is output. Formats in which neither a parity bit nor a
multiprocessor bit is output can also be selected.
One or two 1 bits (stop bits) are output.
Output of 1 bits continues until the start bit of the next
transmit data.
TXI
interrupt
request
Stop
bit
1
453
Start
bit
0
D0
D1
Data
D7
TEI interrupt request
Parity
bit
0/1
Stop
bit
1
Idle (mark)
state
1