D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 165

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3 Operation
7.3.1 Area Division
One of three functions can be selected for the H8/3002 refresh controller: interfacing to
DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval
timing. Table 7-3 summarizes the register settings when these three functions are used.
Table 7-3 Refresh Controller Settings
Register Settings
RFSHCR
RTCOR
RTMCSR
P8DDR
ABWCR
DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR,
RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1.
Set bit P8
ABWCR, make area 3 a 16-bit-access area.
Pseudo-Static RAM Interface: To set up area 3 for connection to pseudo-static RAM, initialize
RTCOR, RTMCSR, and RFSHCR in that order, setting bit PSRAME to 1 and clearing bit
DRAME to 0. Set bit P8
1
DDR to 1 in the port 8 data direction register (P8DDR) to enable CS
SRFMD
PSRAME
DRAME
CAS/WE
M9/M8
RFSHE
RCYCE
CKS2 to CKS0
CMF
CMIE
P8
ABW3
1
DDR
1
DDR to 1 in P8DDR to enable CS
DRAM Interface
Selects self-refresh mode
Cleared to 0
Set to 1
Selects 2CAS or
2WE mode
Selects column
addressing mode
Selects RFSH signal output
Selects insertion of refresh cycles
Refresh interval setting
Set to 1 when RTCNT = RTCOR
Cleared to 0
Set to 1 (CS
Cleared to 0
3
output)
148
PSRAM Interface
Set to 1
Cleared to 0
—
—
—
3
Usage
output.
Interval Timer
Cleared to 0
Cleared to 0
Cleared to 0
—
—
Cleared to 0
—
Interrupt interval setting
Enables or disables
interrupt requests
Set to 0 or 1
—
3
output. In