D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 229

IC H8/3002 ROMLESS 100QFP

D13002F16V

Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of D13002F16V

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 8-9 shows a sample setup procedure for normal mode.
Note: * Carry out settings 1 to 9 with the DEND interrupt masked in the CPU. If an NMI
Set initial destination address
Set initial source address
Set transfer count
Set DTCRB (1)
Set DTCRA (1)
Set DTCRB (2)
Set DTCRA (2)
interrupt occurs during the setup procedure, it may clear the DTME bit to 0,
in which case the transfer will not start.
Read DTCRB
Read DTCRA
Normal mode
Normal mode
Figure 8-9 Normal Mode Setup Procedure (Example)
1
2
3
4
5
6
7
8
9
1.
2.
3.
4.
5.
6.
7.
8.
9.
Set the initial source address in MARA.
Set the initial destination address in MARB.
Set the transfer count in ETCRA.
Set the DTCRB bits as follows.
Set the DTCRA bits as follows.
Read DTCRB with DTME cleared to 0.
Set the DTME bit to 1 in DTCRB.
Read DTCRA with DTE cleared to 0.
Set the DTE bit to 1 in DTCRA to enable the transfer.
213
Clear the DTME bit to 0.
Set the DAID and DAIDE bits to select whether
MARB is incremented, decremented, or held fixed.
Select the DMAC activation source with bits
DTS2B to DTS0B.
Clear the DTE bit to 0.
Select byte or word size with the DTSZ bit.
Set the SAID and SAIDE bits to select whether
MARA is incremented, decremented, or held fixed.
Set or clear the DTIE bit to enable or disable the
CPU interrupt at the end of the transfer.
Clear the DTS0A bit to 0 and set the DTS2A
and DTS1A bits to 1 to select normal mode.

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